For Air-Conditioner Fan Motor
3-Phase Brushless Fan Motor
Driver
BM6209FS
General Description
This motor driver IC adopts PrestoMOS™ as the output
transistor, and put in a small full molding package with
the 180° sinusoidal commutation controller chip and the
high voltage gate driver chip. The protection circuits for
overcurrent, overheating, under voltage lock out and the
high voltage bootstrap diode with current regulation are
built-in. It provides optimum motor drive system and
downsizing the built-in PCB of the motor.
Features
600V
PrestoMOS™ built-in
Output
current 2.5A
Bootstrap
operation by floating high side driver
(including diode)
180°
sinusoidal commutation logic
PWM
control (Upper and lower arm switching)
Phase
control supported from 0° to +40° at 1°
intervals
Rotational
direction switch
FG
signal output with pulse number switch (4 or 12)
VREG
output (5V/30mA)
Protection
circuits provided: CL, OCP, TSD, UVLO,
MLP and the external fault input
Fault
output (open drain)
Applications
Air
conditioners; air purifiers; water pumps;
dishwashers; washing machines
Typical Application Circuit
VDC
GND
VCC
VSP
Key Specifications
Output
MOSFET Voltage:
600V
Driver
Output Current (DC):
±2.5A (Max)
Driver
Output Current (Pulse):
±4.0A (Max)
Output
MOSFET DC On Resistance:
1.7Ω (Typ)
Duty
Control Voltage Range:
2.1V to 5.4V
Phase
Control Range:
0° to +40°
Operating
Case Temperature:
-20°C to +100°C
Junction
Temperature:
+150°C
Power
Dissipation:
3.00W
Package
SSOP-A54_36
W (Typ) x D (Typ) x H (Max)
22.0 mm x 14.1 mm x 2.4 mm
SSOP-A54_36
R1
C1
C2~C4
D1
C5
C6
C7
C13
C8
M
HW
HV
HU
R2
C11
R3
VREG
R4
R11
R9
R13
C9
FG
Q1
DTR
R6
R5
C10
R12
R10
C14
R8
C12
R7
Figure 1. Application Circuit Example
Product
structure : Semiconductor IC
This
product is not designed protection against radioactive rays
.
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BM6209FS
Block Diagram and Pin Configuration
VCC
1
36
35
VSP
TEST
Datasheet
VDC
BU
VCC
VSP
5
6
VREG
VREG
7
VREG
UH
UL
LEVEL
SHIFT
&
GATE
DRIVER
34
U
VCC
GND
GND
GND
VCC
VSP
VREG
NC
HWN
HWP
HVN
HVP
HUN
HUP
PCT
PC
CCW
FGS
FG
FOB
SNS
NC
RT
GND
GND
GND
VCC
VDC
BU
U
HWN
HW
HWP
HVN
HV
HVP
HUN
HU
HUP
PCT
9
10
11
12
13
14
15
V/I
VREG
33
BV
LOGIC
LEVEL
SHIFT
&
GATE
DRIVER
VH
VL
32
V
M
BV
V
31
30
VDC
BW
PC
16
TEST
A/D
VREG
6
WH
WL
VDC
CCW
FGS
VREG
17
18
19
20
VREG
FIB
FAULT
FG
FOB
LEVEL
SHIFT
&
GATE
DRIVER
29
W
28
26
24
PGND
GND
GND
RT
BW
W
FAULT
SNS
21
SINUSOIDAL
WAVE GENE.
VSP
OSC
23
PGND
Figure 2. Block Diagram
Pin Descriptions
(NC: No Connection)
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Name
VCC
GND
GND
GND
VCC
VSP
VREG
NC
HWN
HWP
HVN
HVP
HUN
HUP
PCT
PC
CCW
FGS
FG
FOB
SNS
NC
RT
GND
GND
GND
VCC
Function
Low voltage power supply
Ground
Ground
Ground
Low voltage power supply
Duty control voltage input pin
Regulator output
Hall input pin phase W-
Hall input pin phase W+
Hall input pin phase V-
Hall input pin phase V+
Hall input pin phase U-
Hall input pin phase U+
VSP offset voltage output pin
Phase control input pin
Direction switch (H:CCW)
FG pulse # switch (H:12, L:4)
FG signal output
Fault signal output (open drain)
Over current sense pin
Carrier frequency setting pin
Ground
Ground
Ground
Low voltage power supply
Pin
36
-
Name
VDC
VDC
Figure 3. Pin Configuration
(Top View)
Function
High voltage power supply
35
-
34
BU
U
U
Phase U floating power supply
Phase U output
33
-
32
BV
V
V
Phase V floating power supply
Phase V output
-
31
VDC
VDC
High voltage power supply
30
-
29
BW
W
W
Phase W floating power supply
Phase W output
-
28
PGND
PGND
Ground (current sense pin)
Note) All pin cut surfaces visible from the side of package are no connected, except the pin number is expressed as a “-”.
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BM6209FS
Description of Blocks
Datasheet
1. Commutation Logic
When the hall frequency is about 1.4-Hz or less (e.g. when the motor starts up), the commutation mode is 120° square
wave drive with upper and lower switching (no lead angle). The controller monitors the hall frequency, and switches to
180° sinusoidal commutation drive when the hall frequency reaches or exceeds about 1.4-Hz over four consecutive
cycles. Refer to the timing charts in figures 13 and 14.
Table 1. 120° Commutation (Six-State) Truth Table
HU
H
H
H
L
L
L
HV
L
L
H
H
H
L
HW
H
L
L
L
H
H
UH
L
L
L
PWM
PWM
L
VH
PWM
L
L
L
L
PWM
WH
L
PWM
PWM
L
L
L
UL
H
H
L
--------------------
VL
--------------------
WL
L
--------------------
PWM
L
H
H
L
PWM
PWM
L
H
H
--------------------
PWM
PWM
L
--------------------
--------------------
PWM
2. Duty Control
The switching duty can be controlled by forcing DC voltage with value from V
SPMIN
to V
SPMAX
to the VSP pin. When the
VSP voltage is higher than V
SPTST
, the controller forces PC pin voltage to ground (Testing mode, maximum duty and no
lead angle). The VSP pin is pulled down internally by a 200 kΩ resistor. Therefore, note the impedance when setting the
VSP voltage with a resistance voltage divider.
3. Carrier Frequency Setting
The carrier frequency setting can be freely adjusted by connecting an external
resistor between the RT pin and ground. The RT pin is biased to a constant
voltage, which determines the charge current to the internal capacitor. Carrier
frequencies can be set within a range from about 16 kHz to 50 kHz. Refer to the
formula to the right.
4. FG Signal Output
The number of FG output pulses can be switched in accordance with the number
of poles and the rotational speed of the motor. The FG signal is output from the FG
pin. The 12-pulse signal is generated from the three hall signals (exclusive NOR),
and the 4-pulse signal is the same as hall U signal. It is recommended to pull up
FGS pin to VREG voltage when malfunctioning because of the noise.
f
OSC
[ kHz ]
½
400
R
T
[ kohm ]
FGS
H
L
No. of pulse
12
4
5. Direction of Motor Rotation Setting
The direction of rotation can be switched by the CCW pin. When CCW pin is “H” or
open, the motor rotates at CCW direction. When the real direction is different from
the setting, the commutation mode is 120° square wave drive (no lead angle). It is
recommended to pull up CCW pin to VREG voltage when malfunctioning because
of the noise.
CCW
H
L
Direction
CCW
CW
6. Hall Signal Comparator
The hall comparator provides voltage hysteresis to prevent noise malfunctions. The bias current to the hall elements
should be set to the input voltage amplitude from the element, at a value higher than the minimum input voltage, V
HALLMIN
.
We recommend connecting a ceramic capacitor with value from 100 pF to 0.01 µF, between the differential input pins of
the hall comparator. Note that the bias to hall elements must be set within the common mode input voltage range
V
HALLCM
.
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BM6209FS
Datasheet
7. Output Duty Pulse Width Limiter
Pulse width duty is controlled during PWM switching in order to ensure the operation of internal power transistor. The
controller doesn’t output pulse of less than T
MIN
(0.8µs minimum). Dead time is forcibly provided to prevent external
power transistors to turn-on simultaneously in upper and lower side in driver output (for example, UH and UL) of each
arm. This will not overlap the minimum time T
DT
(1.6µs minimum). Because of this, the maximum duty of 120° square
wave drive at start up is 84% (typical).
8. Phase Control Setting
The driving signal phase can be advanced to the hall signal for phase control. The lead angle is set by forcing DC
voltage to the PC pin. The input voltage is converted digitally by a 6-bit A/D converter, in which internal VREG voltage is
assumed to be full-scale, and the converted data is processed by a logic circuit. The lead angle can be set from 0° to
+40° at 1° intervals, and updated fourth hall cycle of phase W falling edge. Phase control function only operates at
sinusoidal commutation mode. However, the controller forces PC pin voltage to ground (no lead angle) during testing
mode. The VSP offset voltage (Figure 33) is buffered to PCT pin, to connect an external resistor between PCT pin and
ground. The internal bias current is determined by PCT voltage and the resistor value - V
PCT
/ R
PCT
-, and mixed to PC
pin. As a result, the lead angle setting is followed with the duty control voltage, and the performance of the motor can be
improved. Please select the R
PCT
value from 50 kΩ to 200 kΩ in the range on the basis of 100 kΩ, because the PCT pin
current capability is a 100 µA or less.
V
SPMIN
L.A.
VSP
V
PCT
= VSP-V
SPMIN
V
PCT
R
PCT
PCT
L.A.
PC
R
PCL
R
PCT
ADC
VSP
Figure 4. Phase Control Setting Example 1
VREG
VSP
V
SPMIN
L.A.
ADC
V
PCT
= VSP-V
SPMIN
V
PCT
R
PCT
PCT
L.A.
PC
R
PCH
R
PCL
R
PCT
VSP
Figure 5. Phase Control Setting Example 2
9. Current Limiter (CL) Circuit and Overcurrent Protection (OCP) Circuit
The current limiter circuit can be activated by connecting a low value resistor for current detection between the output
stage ground (PGND) and the controller ground (GND). When the SNS pin voltage reaches or surpasses the threshold
value (V
SNS
, 0.5V typical), the controller forces all the upper switching arm inputs low (UH, VH, WH = L, L, L), thus
initiating the current limiter operation. When the SNS pin voltage swings below the ground, it is recommended to insert a
resistor - 1.5 kΩ or more - between SNS pin and PGND pin to prevent malfunction. Since this limiter circuit is not a latch
type, it returns to normal operation - synchronizing with the carrier frequency - once the SNS pin voltage falls below the
threshold voltage. A filter is built into the overcurrent detection circuit to prevent malfunctions, and does not activate when
a short pulse of less than T
MASK
is present at the input.
When the SNS pin voltage reaches or surpasses the threshold value (V
OVER
, 0.9V typical) because of the power fault or
the short circuit except the ground fault, the gate driver outputs low to the gate of all output MOSFETs, thus initiating the
overcurrent protection operation. Since this protection circuit is also not a latch type, it returns to normal operation
synchronizing with the carrier frequency.
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BM6209FS
Datasheet
10. Under Voltage Lock Out (UVLO) Circuit
To secure the lowest power supply voltage necessary to operate the controller and the driver, and to prevent under
voltage malfunctions, the UVLO circuits are independently built into the upper side floating driver, the lower side driver
and the controller. When the supply voltage falls to V
UVL
or below, the controller forces driver outputs low. When the
voltage rises to V
UVH
or above, the UVLO circuit ends the lockout operation and returns the chip only after 32 carrier
frequency periods (1.6ms for the default 20kHz frequency) to normal operation. Even if the controller returns to normal
operation, the output begins from the following control input signal.
The voltage monitor circuit (4.0V nominal) is built-in for the VREG voltage. Therefore, the UVLO circuit does not release
operation when the VREG voltage rising is delayed behind the VCC voltage rising even if VCC voltage becomes V
UVH
or
more.
11. Thermal Shutdown (TSD) Circuit
The TSD circuit operates when the junction temperature of the controller exceeds the preset temperature (125°C
nominal). At this time, the controller forces all driver outputs low. Since thermal hysteresis is provided in the TSD circuit,
the chip returns to normal operation when the junction temperature falls below the preset temperature (100°C nominal).
The TSD circuit is designed only to shut the IC off to prevent thermal runaway. It is not designed to protect the IC or
guarantee its operation in the presence of extreme heat. Do not continue to use the IC after the TSD circuit is activated,
and do not use the IC in an environment where activation of the circuit is assumed.
Moreover, it is not possible to follow the output MOSFET junction temperature rising rapidly because it is a gate driver
chip that monitors the temperature and it is likely not to function effectively.
12. Motor Lock Protection (MLP) Circuit
When the controller detects the motor locking during fixed time of 4 seconds nominal when each edge of the hall signal
doesn't input either, the controller forces all driver outputs low under a fixed time 20 seconds nominal, and self-returns to
normal operation. This circuit is enabled if the voltage force to VSP is over the duty minimum voltage V
SPMIN
, and note
that the motor cannot start up when the controller doesn’t detect the motor rotation by the minimum duty control. Even if
the edge of the hall signal is inputted within range of the OFF state by this protection circuit, it is ignored. But if the VSP
is forced to ground level once, the protection can be canceled immediately.
13. Hall Signal Wrong Input Detection
Hall element abnormalities may cause incorrect inputs that vary from the normal logic. When all hall input signals go high
or low, the hall signal wrong input detection circuit forces all driver outputs low. And when the controller detects the
abnormal hall signals continuously for four times or more motor rotation, the controller forces all driver outputs low and
latches the state. It is released if the duty control voltage VSP is forced to ground level once.
14. Internal Voltage Regulator
The internal voltage regulator VREG is output for the bias of the hall
element and the phase control setting. However, when using the VREG
function, be aware of the I
OMAX
value. If a capacitor is connected to the
ground in order to stabilize output, a value of 1 µF or more should be used.
In this case, be sure to confirm that there is no oscillation in the output.
VCC
VREG
R1
HUP
HU
HUN
HVP
HV
HVN
HWP
HW
HWN
Controller IC
Figure 6. VREG Output Pin Application Example
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TSZ22111 · 15 · 001
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TSZ02201-0828AB400220-1-2
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