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PT7M1233/1233A
Supervisory Circuit
Features
High accurate:
1.5%
(25°
C)
Operating voltage range: 1.0V ~ 5.5V
Operating temperature range: -40° to + 85°
C
C
Detect voltage temperature characteristics:
2.5%
TYP
Output configuration: Bi-dir
Reset timeout period: typical 200ms
Description
The PT7M1233/1233A series are designed to monitor
power supplies in µ and digital systems. They
P
provide excellent circuit reliability and low cost by
eliminating external components and adjustments.
The devices perform a single function: assert a reset
signal whenever the V
CC
supply voltage falls below a
preset threshold. Reset remains asserted 200ms after
V
CC
has risen above the reset threshold.
PT7M1233/1233A are bidirectional output, allowing it
to monitor a pushbutton on the reset output.
Pin Configuration
Pin Description
Name Type
Description
Reset Output and Pushbutton Input:
RST is asserted when V
CC
drops below voltage threshold V
TH-
. Active
low. When other devices pull RST low, the reset condition occurs and will remain a reset timeout period at
least 200ms.
Ground
Supply Voltage.
RST
I/O
GND
VCC
P
P
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PT7M1233/1233A
Supervisory Circuit
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Maximum Ratings
Storage Temperature ............................................................-65
o
C to +150
o
C
Ambient Temperature with Power Applied .......................... -40
o
C to +85
o
C
Supply Voltage to Ground Potential (Vcc to GND) ..............-0.3V to +7.0V
DC Input Voltage (All inputs except Vcc and GND)......-0.3V to V
CC
+0.3V
DC Output Current (All outputs) ..........................................................30mA
Power Dissipation .......................................... 320mW (Depend on package)
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other condi-
tions above those indicated in the operational sec-
tions of this specification is not implied. Exposure
to absolute maximum rating conditions for extended
periods may affect reliability.
DC Electrical Characteristics
(T
A
= -40~85º unless otherwise noted. Typical values are at T
A
= +25º
C,
C)
Description
Supply Voltage
Supply Current
Sym.
V
CC
V
CC
= 5.5V. No load.
I
CC
V
CC
= 3.6V. No load.
+25C
Voltage Threshold
V
TH-
-40C~85C
Voltage Threshold
(PT7M1233A-10)
+25C
V
TH-
-40C~85C
+25C
V
TH-
-40C~85C
V
HYS
V
TH+
- V
TH-*
I
OH
= 8mA, V
CC
= 5V
Output
Driving
Output low
V
OL
I
OH
= 4mA, V
CC
= 3V
I
OH
= -50µ V
CC
= 1V
A,
-
(V
TH-
)
0.985
(V
TH-
)
0.975
(V
TH-
)
0.985
(V
TH-
)
0.975
(V
TH-
)
0.985
(V
TH-
)
0.975
-
-
-
-
-
V
TH-
V
TH-
2.88
2.88
2.72
2.72
50
-
-
-
10
(V
TH-
)
1.015
(V
TH-
)
1.025
(V
TH-
)
1.015
(V
TH-
)
1.025
(V
TH-
)
1.015
(V
TH-
)
1.025
-
0.4
0.3
0.09
V
µA
V
V
V
V
V
V
mV
Test Conditions
Min
1.0
-
Typ
-
-
Max
5.5
12
Unit
V
µA
Voltage Threshold
(PT7M1233A-15)
Hysteresis
Note:
V
TH-
is voltage threshold when V
CC
falls from high to low. V
TH+
is voltage threshold when V
CC
rises from low to high.
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PT7M1233/1233A
Supervisory Circuit
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AC Electrical Characteristics
Timing diagram
t
SEN
VCC
V
RST
1V
0V
t
RS
t
RPD
t
RS
RST
1V
0V
V
RST
VCC
1V
0V
t
RS
t
PD
t
RS
RST
0.8V
CC
1V
0.8V
0V
Uncertain state
External pull down
signal release
Note: If t
PD
< t
RS
, the reset pulse width will be t
RS
; if t
PD
> t
RS
, the width will be t
PD
+ t
RS
.
(V
CC
= 1.0V to 5.5V, T
A
= -40~85º unless otherwise noted. Typical values are at T
A
= +25º
C,
C)
Sym.
t
RS
t
RPD
t
SEN
t
PD
Description
Reset Timeout Period
Delay
Sensitivity
External Pull Down Signal Pulse
Pushbutton Debounce
Pushbutton Detect*
-
-
-
RST pin
RST pin
Test Conditions
Min
140
-
20
1
140
0.8
Typ
200
17
-
-
200
1.5
Max
280
-
-
-
280
2.0
Unit
ms
s
s
s
ms
V
RST pin
*Note: RST will be asserted when it is pull down to the typical value or less.
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Supervisory Circuit
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Block Diagram
Vcc
Reset
Monitor
VCC Resistor
Divider
Timing
Delay
T.C.
Reference
5k
RST
GND
Function Description
Power Monitor
A microprocessor’s (µP’s) reset input starts the µP in a known state. Whenever the µ is in an unknown state, it should be held in
P
reset. The supervisory circuits assert reset during power-up and prevent code execution errors during power-down or brownout
conditions.
On power-up, once Vcc reaches about 1.0V, RST is a guaranteed logic low of 0.4V or less. As Vcc rises, RST stays low. When
Vcc rises above the reset threshold V
RST
, an internal timer releases RST after about 200ms. RST asserts whenever Vcc drops
below the reset threshold, i.e. brownout condition. If brownout occurs in the middle of a previously initiated reset pulse, the pulse
continues for at least another 200ms. On power-down, once Vcc falls below the reset threshold, RST stays low and is guaranteed
to be 0.4V or less until Vcc drops below 1V.
Reset Output: Bi-direction
PT7M1233
The devices provide RST output pin for a pushbutton switch. When the devices are not in a reset cycle, it continuously monitors
the RST signal for a low going edge. If an edge is detected, the devices will debounce the switch by pulling the RST line low.
After the internal timer has expired, the devices will continue to monitor the RST line. If the line is still low, they will continue to
monitor the line looking for a rising edge. Upon detecting a release, they will force the RST line low and hold it low for 200ms.
PT7M1233A
When an out-of-tolerance condition is detected, an internal power fail signal is generated which forces reset to the active state.
When V
CC
returns to an in-tolerance condition, the reset signal is kept in the active state for approximately 200ms to allow the
power supply and processor to stabilize. The second function of the PT7M1233A is pushbutton reset control. The PT7M1233A
debounces a pushbutton closure and will generate a 200ms reset pulse upon release.
2013-06-0001
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PT7M1233/1233A
Supervisory Circuit
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Application Information
Typical Operation Circuit
PT7M1233 Application Example
Vcc
RST
PT7M1233/1233A
MICROPROCESSOR
RESET
2013-06-0001
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PT0195-4
06/17/13
FPGA/CPLD
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