PT7C4502
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PLL Clock Multiplier
Features
Low cost frequency multiplier
Zero ppm multiplication error
Input crystal frequency of 5 - 30 MHz
Input clock frequency of 4 - 50 MHz
Output clock frequencies up to 180 MHz
Period jitter 50ps (100~180MHz)
Duty cycle of 45/55% up to 160MHz
Operating voltages of 3.0 to 5.5V
Tri-state output for board level testing
Die form, Wafer form
Description
The PT7C4502 is a high performance frequency
multiplier, which integrates Analog Phase Lock Loop
techniques.
The PT7C4502 is the most cost effective way to
generate a high quality, high frequency clock output
from a lower frequency crystal or clock input. It is
designed to replace crystal oscillators in most electronic
systems, clock multiplier and frequency translation.
Using Phase-Locked-Loop (PLL) techniques, the
device uses a standard fundamental mode, inexpensive
crystal to produce output clocks up to 180 MHz.
The complex Logic divider is the ability to
generate nine different popular multiplication factors,
allowing one chip to output many common frequencies.
Applications
Used for crystal oscillator
The device also has an Output Enable pin that tri-
states the clock output when the OE pin is taken low.
This product is intended for clock generation and
frequency translation with low output jitter (variation in
the output period)
Block Diagram
S0
S1
PLL Clock Synthesis
and
Control Circuit
Output
Buffer
CLK
X1/ICLK
X2
Crystal
Oscillator
V
CC
GND
2014-09-0002
1
PT0140-6
09/23/14
PT7C4502
PLL Clock Multiplier
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Pin/Pad Configuration
1520um
OE
X1 -ICLK
AVDD
DVDD
1100um
Part No.
X2
S1
AGND
DGND
CLK
S0
Pin/Pad Description
Pin Name
X1/ICLK
Pad Name
X1-ICLK
X2
S0
S1
OE
CLK
VCC
GND
AVDD
DVDD
AGND
DGND
Type
I
O
I
I
I
O
P
P
P
P
Description
Crystal connection or clock input.
Crystal connection. Leave unconnected for clock input.
Multiplier select pin 0. Connect to Vcc or float.
Multiplier select pin 1. Connect to GND or float. Internal pull-up.
Output Enable. Tri-states CLK output when low.
Clock output.
Analog Power.
Digital power.
Analog Ground
Digital ground.
Pad Coordinate File
Pad Name
X Coordinate
Y Coordinate
Pad Name
X Coordinate
Y Coordinate
X1-ICLK
120.90
892.90
CLK
1098.90
118.60
X2
120.90
641.50
S0
1322.10
118.60
S1
117.70
401.10
DVDD
1303.50
973.30
AGND
111.50
225.80
AVDD
1063.10
973.30
DGND
698.40
118.60
OE
470.70
981.70
Note:
Substrate is connected to GND.
Die Size:
1670m*1180m (Including scribe line size 150m*80m.)
Die Thickness:
PT7C4502DE: 35025m without coating; PT7C4502-2WF: 22020m with coating
Pad Size:
75m*75m
S1
0
0
Note 3
S0
M
Note 2
1
Note 2
1
M
Note 3
1
1
Note 1: CLK output frequency=ICLK×
2;
2. M=Leave unconnected (self-biases to Vcc/2);
3. Internal pull-up on S1, unconnected = 1
2014-09-0002
2
CLK
×
Note 1
2
×
3
(default)
×
4
×
5
PT0140-6
09/23/14
PT7C4502
PLL Clock Multiplier
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External Components
Decoupling Capacitor
As with any high-performance mixed-signal IC, the
PT7C4502 must be isolated from system power supply
noise to perform optimally. A decoupling capacitor of
0.01μF or 0.1uF must be connected between VCC and
the GND. It must be connected close to the PT7C4502
to minimize lead inductance. No external power supply
filtering is required for the PT7C4502.
Series Termination Resistor
A 33Ω terminating resistor can be used next to the
CLK pin for trace lengths over one inch.
Crystal Load Capacitors
There is no on-chip capacitance build-in chip. A
parallel resonant, fundamental mode crystal should be
used. The device crystal connections should include
pads for small capacitors from X1 to ground and from
X2 to ground. These capacitors are used to adjust the
stray capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
between the crystal and device. Crystal capacitors, if
needed, must be connected from each of the pins X1
and X2 to ground. The value (in pF) of these crystal
caps should equal C
L
*2. In this equation, C
L
= crystal
load capacitance in pF. Example: For a crystal with a 15
pF load capacitance, each crystal capacitor would be
30pF.
Maximum Ratings
Storage Temperature ................................................................................... -65oC to +150oC
Supply Voltage to Ground Potential (V
CC
).................................................-0.3V to + 7.0V
Inputs(Reference to GND)
............................................. -0.5V to
Vcc
+ 0.5V
Clock Output (Reference to GND) .........................
-0.5V to
Vcc
+ 0.5V
Soldering Temperature (Max of 10 seconds) .............................. 260
O
C
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other condi-
tions above those indicated in the operational sec-
tions of this specification is not implied. Exposure
to absolute maximum rating conditions for extended
periods may affect reliability.
Recommended operation conditions
Symbol
T
A
V
DD
Description
Operation Temperature
Min
-40
Type
-
Max
+85
Unit
C
Supply voltage
3.0
-
5.5
V
2014-09-0002
3
PT0140-6
09/23/14
PT7C4502
PLL Clock Multiplier
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DC Electrical Characteristics
(V
CC
= 3.3V±0.3V, T
A
= -40 ~ 85º unless otherwise noted)
C,
Sym.
Vcc
Icc
V
IH
V
IL
V
IH
V
IM
V
IL
V
OH
V
OL
I
S
I
I
Parameter
Supply Voltage
Supply Current
Input Logic High
Input Logic Low
Input Logic High
Input mid-level
Input Logic Low
High-level output voltage
Low-level output voltage
Short Circuit Current
Input Leakage Current
-
S1
-
-
no load, 20MHz crystal,
OE = Vcc
-
-
-
-
-
I
OH
= -12mA
I
OL
= 12mA
-
-
Test Condition
Pin
Vcc
Vcc
ICLK, OE
ICLK, OE
S0, S1
S0, S1
S0, S1
CLK
CLK
CLK
OE
Min.
3
-
2
-
Vcc-0.5
-
-
2.4
-
-
-
Typ.
3.3
12
-
-
-
Vcc/2
-
-
-
30
-7.5
Max.
3.6
20
-
0.8
-
-
0.5
-
0.4
-
1
-20
Unit
V
mA
V
V
V
V
V
V
V
mA
A
A
(V
CC
= 5.0V±0.5V, T
A
= -40 ~ 85º unless otherwise noted)
C,
Sym.
Vcc
Icc
V
IH
V
IL
V
IH
V
IM
V
IL
V
OH
V
OL
I
S
I
I
Parameter
Supply Voltage
Supply Current
Input Logic High
Input Logic Low
Input Logic High
Input mid-level
Input Logic Low
High-level output voltage
Low-level output voltage
Short Circuit Current
Input Leakage Current
-
S1
-
-
no load, 20MHz crystal,
OE = Vcc
-
-
-
-
-
I
OH
= -12mA
I
OL
= 12mA
-
-
Test Condition
Pin
Vcc
Vcc
ICLK, OE
ICLK, OE
S0, S1
S0, S1
S0, S1
CLK
CLK
CLK
OE
Min.
4.5
-
0.65Vcc
-
Vcc-0.4
-
-
Vcc-0.5
-
-
-
Typ.
5.0
20
-
-
-
Vcc/2
-
-
-
70
-7.5
Max.
5.5
30
-
0.8
-
-
0.4
-
0.4
-
1
-20
Unit
V
mA
V
V
V
V
V
V
V
mA
A
A
2014-09-0002
4
PT0140-6
09/23/14
PT7C4502
PLL Clock Multiplier
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AC Electrical Characteristics
(V
CC
= 3.3V±0.3V, T
A
= -40 ~ 85º unless otherwise noted)
C,
Sym.
f
IN
f
OUT
t
r
t
f
Duty
Parameter
Input Frequency
Output frequency
Output clock rise time
Output clock fall time
Output clock duty cycle
PLL bandwidth
Output enable time
Output disable time
Period Jitter
Test Condition
Crystal
Vcc: 3.0 to 3.6V
0.8 to 2.0V, 15pF load
2.0 to 0.8V, 15pF load
At Vcc/2, below
160MHz
At Vcc/2, 160MHz to
180MHz
-
OE high to output on
OE low to tri-state
100MHz~180MHz
Pin
ICLK
CLK
CLK
CLK
CLK
CLK
-
-
-
CLK
Min.
5
20
-
-
45
40
10
-
-
-
-
-
-
50
Typ.
-
-
1
1
50
Max.
30
180
-
-
55
60
-
50
50
100
Unit
MHz
MHz
ns
ns
%
%
kHz
ns
ns
ps
(V
CC
= 5.0V±0.5V, T
A
= -40 ~ 85º unless otherwise noted)
C,
Sym.
f
IN
f
OUT
t
r
t
f
Parameter
Input Frequency
Output frequency
Output clock rise time
Output clock fall time
Test Condition
Crystal
Vcc: 4.5 to 5.5V
20%Vcc to 80%Vcc,
15pF load
20%Vcc to 80%Vcc,
15pF load
At Vcc/2, below
160MHz
At Vcc/2, 160MHz to
180MHz
-
OE high to output on
OE low to tri-state
100MHz~180MHz
Pin
ICLK
CLK
CLK
CLK
CLK
CLK
-
-
-
CLK
Min.
5
20
-
-
45
40
10
-
-
-
-
-
-
50
Typ.
-
-
1.2
1.2
50
Max.
30
180
-
-
55
60
-
50
50
100
Unit
MHz
MHz
ns
ns
%
%
kHz
ns
ns
ps
Duty
Output clock duty cycle
PLL bandwidth
Output enable time
Output disable time
Period Jitter
Test circuits
1>Load circuit for output clock duty cycle, rise and fall time Measurement
33om
From Output
Under Test
15pF
2>Timing Definitions for output clock rise and fall time Measurement
2014-09-0002
5
PT0140-6
09/23/14
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