DS1963S
SHA iButton
www.iButton.com
SPECIAL FEATURES
§
§
§
§
4096 bits of read/write nonvolatile (NV)
memory organized as 16 pages of 256 bits
each
Eight memory pages with individual 64-bit
secrets and 32-bit read-only non rolling-over
page write cycle counters
Secrets are write-only and have their own
individual write cycle counters
On-chip 512-bit SHA-1 (FIPS 180-1,
ISO/IEC 10118-3) engine to compute a 160-
bit Message Authentication Codes (MAC)
and generate page secrets
Device can operate as roaming iButton
®
or
as coprocessor for a host computer
256–bit scratchpad ensures integrity of data
transfer
On-chip 16-bit CRC generator for
safeguarding data transfers
Overdrive mode boosts communication
speed to 125 kbits per second
Operating temperature range from -20°C to
+85°C
Over 10 years of data retention
§
§
§
§
§
§
§
§
§
§
§
§
Button shape is self-aligning with cup-
shaped probes
Durable stainless steel case engraved with
registration number withstands harsh
environments
Easily affixed with self-stick adhesive
backing, latched by its flange, or locked with
a ring pressed onto its rim
Presence detector acknowledges when reader
first applies voltage
Meets UL#913 (4th Edit.); Intrinsically Safe
Apparatus, Approved under Entity Concept
for use in Class I, Division 1, Group A, B, C
and D Locations (application pending)
F5 MicroCan
5.89
0.51
â
16.25
000000FBC52B
1-Wire
â
51
â
18
17.35
COMMON iButton FEATURES
Unique, factory–lasered and tested 64-bit
registration number (8-bit family code
+ 48-bit serial number + 8-bit CRC tester)
assures absolute traceability because no two
parts are alike
Multidrop controller for MicroLAN
Digital identification and information by
momentary contact
Chip-based data carrier compactly stores
information
Data can be accessed while affixed to object
Economically communicates to host with a
single digital signal at 15.4 kbits per second
Standard 16 mm diameter and 1-Wire
®
protocol ensure compatibility with iButton
Device family
IO
GND
All dimensions are shown in millimeters
§
§
§
§
§
§
ORDERING INFORMATION
DS1963S
F5 MicroCan
EXAMPLES OF ACCESSORIES
DS9096P
DS9101
DS9093RA
DS9093A
DS9092
Self-Stick Adhesive Pad
Multipurpose Clip
Mounting Lock Ring
Snap-In Fob
iButton Probe
iButton and 1-Wire are registered trademarks of Dallas Semiconductor.
1 of 37
021704
DS1963S
iButton DESCRIPTION
The DS1963S Monetary iButton with SHA-1 Function is a rugged 4 kbit read/write data carrier that can
be easily accessed with minimal hardware. Its NV memory acts as a localized database for public as well
as protected data belonging to the owner of the device and the environment in which it is used. An
integrated 512-bit SHA-1 engine can be activated to compute 160-bit message authentication codes
(MAC) based on information stored in the device. Data is transferred serially via the 1-Wire protocol,
which requires only a single data lead and a ground return. Using the TMEX file format (see Application
Note 114) a single DS1963S can serve up to four independent applications, such as secure change purses
for electronic payment at local transit systems, pay phones, parking systems or vending machines. The
DS1963S is also intended to function as a coprocessor that assists the host in computing signatures, using
a secure signing secret, when writing back the new balance to a roaming device after a purchase.
The DS1963S, like other SRAM-based iButtons, has an additional memory area called the scratchpad that
acts as a buffer when writing to the main memory. The DS1963’s scratchpad is also used for feeding data
segments to the SHA-1 engine or receiving/comparing message authentication codes.
Data is first written to the scratchpad from where it can be read back. After the data has been verified, a
copy scratchpad command will transfer the data to main memory. This process ensures data integrity in
an environment that does not provide a reliable electric contact.
Each DS1963S has its own 64-bit ROM registration number that is factory lasered into the chip inside to
provide a guaranteed unique identity for absolute traceability. The durable MicroCan package is highly
resistant to environmental hazards such as dirt, moisture, and shock. Its compact coin-shaped profile is
self-aligning with mating receptacles, allowing the DS1963S to be easily used by human operators.
Accessories permit the DS1963S to be mounted on almost any surface including plastic key fobs, photo-
ID badges and printed circuit boards.
SECURITY
A system that uses mobile data carriers consists mainly of three components, 1) host computers that read
and write data carriers, 2) the data carriers (“slave devices”) themselves, and 3) the users of the system
who might be tempted to manipulate the data or to emulate the behavior of the data carrier. The DS1963S
is designed to address all these areas of attacks without using any proprietary restricted algorithms. The
security of the device is based on the Secure Hash Standard SHA-1, which is documented on the Internet
at locations such as http://www.itl.nist.gov/div897/pubs/fip180-1.htm.
The table below shows a matrix of possible non-violent attacks in form of a truth table. The notes
referenced in the table explain the typical methods to defeat the attacks. A more detailed description is
found in the section “Application Overview” near the end of this document. For the full description of the
functions used see section “Memory and SHA Function Commands” and the SHA-1 Computation and
message formats.
Authorized
Host
Unauthorized
Host
Authentic data
See note 2
Normal operation
See note 1
Don’t care
Manipulated data
See notes 2 and 3
See note 3
Don’t care
Don’t care
Emulated slave
Authentic
Slave
Emulated slave
2 of 37
DS1963S
Note 1: The device provides functions to authenticate the host based on a system-wide secret, the
device’s ROM Registration number and a user-selected pin number that is installed in one of the
memory pages of a roaming data carrier.
Note 2: To find out whether a slave device is authentic the host writes a 3-byte “challenge” to the
scratchpad before issuing a command to compute the SHA-1 MAC over the challenge, the data
of a memory page, the page number, the page’s write-cycle counter, the device’s ROM
Registration number, and the secret associated with that page. By varying the challenge every
time it reads from a slave, the host can verify that the slave contains the correct secret and can
perform the required SHA computation in the required time.
Note 3: Manipulated data can be discovered if the data in the slave device is “signed” by an authorized
host. Signing consists of calculating a 160-bit SHA-1 MAC over the data to be protected, the
write-cycle counter of the page on which it is to be stored, the ROM ID of the slave device in
which it is to be stored, and any dedicated secret known only to authorized hosts. The MAC is
stored together with the application data (a monetary value together with a transaction ID code,
for example) in an appropriate memory page. To verify the authenticity of the data the host
repeats the process of signing. Any change in the data, the cycle counter, data carrier or an
invalid (not belonging to the system) signing-secret will make the verification of the signature
fail.
OVERVIEW
The block diagram in Figure 1 shows the relationships between the major control and memory sections of
the DS1963S. The DS1963S has six main data components: 1) 64-bit lasered ROM, 2) 256-bit scratch-
pad, 3) eight 32-byte pages of general-purpose SRAM, 4) eight 32-byte pages of SRAM protected by
write-cycle counters, 5) two 32-byte pages storing eight 64-bit secrets with individual write-cycle
counters, and 6) a 512-bit SHA-1 Engine (SHA = Secure Hash Algorithm). The hierarchical structure of
the 1-Wire protocol is shown in Figure 2. All write-cycle counters are 32 bits long and will not roll over
once the maximum count has been reached. The contents of the counters is read together with the
memory data using a special command. The bus master must first provide one of the seven ROM
Function Commands, 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Skip ROM, 5) Resume
Communication, 6) Overdrive-Skip ROM or 7) Overdrive-Match ROM. Upon completion of an
Overdrive ROM command byte executed at standard speed, the device will enter Overdrive mode where
all subsequent communication occurs at a higher speed. The protocol required for these ROM function
commands is described in Figure 10. After a ROM function command is successfully executed, the
memory functions become accessible and the master may provide any one of the eight memory function
commands. The protocol for these memory function commands is described in Figure 7. All data is read
and written least significant bit first.
PARASITE POWER
The block diagram (Figure 1) shows the parasite-powered circuitry. This circuitry “steals” energy
whenever the data contact is in the logic-high state. This stolen energy will provide sufficient power
while the data contact is in a logic-low state as long as the specified timing and voltage requirements are
met. The advantages of parasite power are two-fold: 1) by stealing energy off this input, the DS1963S-
internal lithium reserves are conserved and 2) if the lithium is exhausted for any reason, the ROM may
still be read normally. The remaining circuitry of the DS1963S is solely operated by lithium energy.
3 of 37
DS1963S
64-BIT LASERED ROM
Each DS1963S contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family
code. The next 48 bits are a unique serial number. The last 8 bits are a CRC of the first 56 bits.
(See Figure 3). The 1-Wire CRC is generated using a polynomial generator consisting of a shift register
8
5
4
and XOR gates as shown in Figure 4. The polynomial is X + X + X + 1. Additional information about
the Dallas 1-Wire Cyclic Redundancy Check is available in the
Book of DS19xx iButton Standards.
The
shift register bits are initialized to zero. Then starting with the least significant bit of the family code, one
bit at a time is shifted in. After the 8th bit of the family code has been entered, then the serial number is
entered. After the 48th bit of the serial number has been entered, the shift register contains the CRC
value. Shifting in the 8 bits of CRC should return the shift register to all zeros.
DS1963S BLOCK DIAGRAM
Figure 1
DATA
1-Wire
Function Control
Lid
Contact
Flag and Mode
Register
64-bit
Lasered ROM
Parasite-Powered
Circuitry
Memory and
SHA Function
Control Unit
512-bit
Secure Hash
Algorithm
Engine (SHA-1)
PRNG
Counter
CRC16
Generator
256-bit
Scratchpad
R
Data Memory
8 Pages of
256 bits each
S
Data Memory
8 Pages of
256 bits each
8 Write-Cycle
Counters
one for each
Memory Page
8 Write-Cycle
Counters
one for each
Secret
Secrets Memory
2 Pages of
256 bits
storing 8 Secrets
of 64 bits each
4 of 37
DS1963S
HIERARCHCAL STRUCTURE FOR 1-WIRE PROTOCOL
Figure 2
Bus
Master
1-Wire Bus
Other
Devices
DS1963S
Command
Level
Available
Commands
Read ROM
Match ROM
Search ROM
Skip ROM
Resume
Overdrive Skip
Overdrive Match
Write Scratchpad
Read Scratchpad
Copy Scratchpad
Match Scratchpad
Erase Scratchpad
Read Memory
Read Authenti-
cated Page
Compute SHA
Data Fields
Affected
64-bit ROM, RC-Flag
64-bit ROM, RC-Flag
64-bit ROM, RC-Flag
RC-Flag
RC-Flag
64-bit ROM, RC-Flag, OD-Flag
64-bit ROM, RC-Flag, OD-Flag
256-bit Scratchpad, Flags
256-bit Scratchpad, HIDE Flag
Data Memory, Secrets Memory,
W/C Counter, Flags
160 bits of Scratchpad, Flags
256-bit Scratchpad, Flags
Data Memory, Flags
Data Memory, W/C Counters of
Memory Page and Secret, Secret, 64-
bit ROM Registration Number, 160 bits
of Scratchpad, Flags, PRNG Counter
Several of the following Items,
depending on selected Sub-Function:
Data Memory, W/C Counter of
Memory Page, Secret, 64-bit ROM
Registration Number, Scratchpad,
Flags, PRNG Counter
1-Wire ROM Function
Commands (see Figure 10)
DS1963S specific
Memory Function
Commands (see Figure 7)
64-BIT LASERED ROM
Figure 3
MSB
8-Bit CRC Code
MSB
LSB
MSB
48-Bit Serial Number
LSB
LSB
8-Bit Family Code (18h)
MSB
LSB
5 of 37
模拟与混合信号
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
