Datasheet> 器件分类 > 无源元件> 振荡器> SIT5146AECFA628JFA19.123456

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SIT5146AECFA628JFA19.123456: 产品描述Clipped Sine Output Oscillator, 19.123456MHz Nom,; 产品类别无源元件振荡器; 文件大小2MB，共36页; 制造商SiTime; 标准

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SIT5146AECFA628JFA19.123456概述

Clipped Sine Output Oscillator, 19.123456MHz Nom,

SIT5146AECFA628JFA19.123456规格参数

参数名称	属性值
是否Rohs认证	符合
包装说明	LCC10,.13X.2,58/52/48
Reach Compliance Code	unknown
老化	1 PPM/YEAR
最长下降时间	1.9 ns
频率调整-机械	NO
频率稳定性	1%
安装特点	SURFACE MOUNT
端子数量	10
标称工作频率	19.123456 MHz
最高工作温度	105 °C
最低工作温度	-40 °C
振荡器类型	CLIPPED SINE
输出阻抗	18 Ω
输出负载	15 pF
封装主体材料	CERAMIC
封装等效代码	LCC10,.13X.2,58/52/48
物理尺寸	5.15mm x 3.35mm x 1.06mm
最长上升时间	1.9 ns
最大压摆率	53 mA
最大供电电压	3.08 V
最小供电电压	2.52 V
标称供电电压	2.8 V
表面贴装	YES
最大对称度	55/45 %

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SiT5146

PRELIMINARY

1 MHz to 60 MHz, ±0.5 to ±2.5 ppm, Endura™ Series Super-TCXO

Description

The

SiT5146

is a ruggedized ±0.5 to ±2.5 ppm MEMS

Features



Super-TCXO with a maximum acceleration sensitivity of

0.009 ppb/g or 0.1 ppb/g. Engineered for best dynamic

performance, it is ideal for high reliability telecom, wireless

and networking, industrial, precision GNSS and

audio/video applications.

Leveraging SiTime’s unique DualMEMS™ temperature

sensing and TurboCompensation™ technologies, the

SiT5146 delivers the best dynamic performance for timing

stability in the presence of environmental stressors due to

air flow, temperature perturbation, vibration, shock, and

electromagnetic interference. This device also integrates

multiple on-chip regulators to filter power supply noise,

eliminating the need for a dedicated external LDO.

The SiT5146 offers three device configurations that can be

ordered using

Ordering Codes

for:

1) TCXO with non-pullable output frequency,

2) VCTCXO allowing voltage control of output

frequency, and

3) DCTCXO, enabling digital control of output frequency

using an I

C interface, pullable to 5 ppt (parts per

trillion) resolution.

The SiT5146 can be factory programmed for any

combination of frequency, stability, voltage, and pull range.

Programmability enables designers to optimize clock

configurations while eliminating long lead times and

customization costs associated with quartz devices where

each frequency is custom built.

Refer to

Manufacturing Guideline

for proper reflow profile

and PCB cleaning recommendations to ensure best

performance.



Any frequency from 1 MHz to 60 MHz in 1 Hz steps

Factory programmable options for low lead times

Best dynamic stability under airflow, thermal shock



0.009 ppb/g or 0.1 ppb/g acceleration sensitivity



±0.5 ppm stability across temperature



±15 ppb/C typical frequency slope (ΔF/ΔT)

-40°C to +105°C operating temperature

No activity dips or micro jumps

Resistant to shock, vibration and board bending

On-chip regulators eliminate the need for external LDOs

Digital frequency pulling (DCTCXO) via I



Digital control of output frequency and pull range



Up to

±3200

ppm pull range



Frequency pull resolution down to 5 ppt

2.5V, 2.8V, 3.0V and 3.3V supply voltage

LVCMOS or clipped sinewave output

RoHS and REACH compliant

Pb-free, Halogen-free, Antimony-free

Applications



Ballistics, missiles, munitions

Military portable radios

Ruggedized communications networks

Precision GNSS systems

SATCOM

Transponders

Military, defense, space, avionics systems

Block Diagram

5.0 x 3.2 mm

Package Pinout

SDA / NC

OE / VC / NC

SCL / NC

GND

VDD

CLK

A0 / NC

Figure 1. SiT5146 Block Diagram

Figure 2. Pin Assignments (Top view)

(Refer to

Table 13

for Pin Descriptions)

Rev 0.52

July 22, 2019

www.sitime.com

SiT5146

1 MHz to 60 MHz, ±0.5 to ±2.5 ppm, Endura™ Series Super-TCXO

TABLE OF CONTENTS

PRELIMINARY

Description ................................................................................................................................................................................... 1

Features....................................................................................................................................................................................... 1

Applications ................................................................................................................................................................................. 1

Block Diagram ............................................................................................................................................................................. 1

5.0 x 3.2 mm

Package Pinout ..................................................................................................................................................... 1

Ordering Information .................................................................................................................................................................... 2

Electrical Characteristics.............................................................................................................................................................. 4

Device Configurations and Pin-outs ............................................................................................................................................. 9

Pin-out Top Views................................................................................................................................................................. 9

Test Circuit Diagrams for LVCMOS and Clipped Sinewave Outputs ......................................................................................... 10

Waveforms................................................................................................................................................................................. 12

Timing Diagrams ........................................................................................................................................................................ 13

Typical Performance Plots ......................................................................................................................................................... 14

Architecture Overview ................................................................................................................................................................ 16

Frequency Stability ............................................................................................................................................................. 16

Output Frequency and Format ............................................................................................................................................ 16

Output Frequency Tuning ................................................................................................................................................... 16

Pin 1 Configuration (OE, VC, or NC) .................................................................................................................................. 17

Device Configurations ................................................................................................................................................................ 17

TCXO Configuration ........................................................................................................................................................... 17

VCTCXO Configuration ...................................................................................................................................................... 18

DCTCXO Configuration ...................................................................................................................................................... 19

VCTCXO-Specific Design Considerations ................................................................................................................................. 20

Linearity .............................................................................................................................................................................. 20

Control Voltage Bandwidth ................................................................................................................................................. 20

FV Characteristic Slope K

................................................................................................................................................. 20

Pull Range, Absolute Pull Range ........................................................................................................................................ 21

DCTCXO-Specific Design Considerations ................................................................................................................................. 22

Pull Range and Average Pull Range .................................................................................................................................. 22

Output Frequency ............................................................................................................................................................... 23

C Control Registers .......................................................................................................................................................... 25

Register Descriptions.......................................................................................................................................................... 25

Register Address: 0x00. Digital Frequency Control Least Significant Word (LSW) ............................................................ 25

Register Address: 0x01. OE Control, Digital Frequency Control Most Significant Word (MSW) ......................................... 26

[14]

....................................................................................... 27

Serial Interface Configuration Description .......................................................................................................................... 28

Serial Signal Format ........................................................................................................................................................... 28

Parallel Signal Format ........................................................................................................................................................ 29

Parallel Data Format ........................................................................................................................................................... 29

C Timing Specification ...................................................................................................................................................... 31

C Device Address Modes ................................................................................................................................................. 32

Schematic Example ............................................................................................................................................................ 33

Dimensions and Patterns ........................................................................................................................................................... 34

Layout Guidelines ...................................................................................................................................................................... 35

Manufacturing Guidelines .......................................................................................................................................................... 35

Additional Information ................................................................................................................................................................ 36

Revision History ......................................................................................................................................................................... 36

Rev 0.52

Page 3 of 36

www.sitime.com

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