Si8920
I
S O L A T E D
A
M P L I F IE R
Features
FOR
C
URRENT
S
HUNT
M
EASUREMENT
Low voltage differential input
±100
mV and ±200 mV options
Low signal delay: 0.75 µs
Input offset: 0.2 mV
Gain error: <0.5%
Excellent drift specifications
1
Low noise: 0.10 mVrms over
100 kHz bandwidth
High common-mode transient
immunity: 75 kV/µs
Compact packages
wide body SOIC
8-pin surface mount DIP
–40 to 125 °C
AEC-Q100
16-pin
µV/°C offset drift
60 ppm/°C gain drift
Nonlinearity: 0.1% full-scale
Applications
Industrial, HEV and renewable
energy inverters
AC, Brushless, and DC motor
controls and drives
Variable speed motor control in
consumer white goods
Isolated switch mode and UPS
power supplies
Ordering Information:
See page 14.
Safety Approvals (Pending)
UL 1577 recognized
Up
VDE certification conformity
VDE0884
to 5000 Vrms for 1 minute
CSA component notice 5A
approval
Part 10
(basic/reinforced insulation)
Pin Assignments
VDDA
1
AIP
2
AIN
3
GNDA
4
8
CQC certification approval
GB4943.1
VDDB
Description
The Si8920 is a galvanically isolated analog amplifier. The low-voltage
differential input is ideal for measuring voltage across a current shunt
resistor or for any place where a sensor must be isolated from the control
system. The output is a differential analog signal amplified by either 8.1x
or 16.2x.
The very low signal delay of the Si8920 allows control systems to respond
quickly to fault conditions or changes in load. Low offset and gain drift
ensure that accuracy is maintained over the entire operating temperature
range. Exceptionally high common-mode transient immunity means that
the Si8920 delivers accurate measurements even in the presence of high-
power switching as is found in motor drive systems and inverters.
The Si8920 isolated amplifier utilizes Silicon Labs’ proprietary isolation
technology. It supports up to 5.0 kVrms withstand voltage per UL1577.
This technology enables higher performance, reduced variation with
temperature and age, tighter part-to-part matching, and longer lifetimes
compared to other isolation technologies.
Si8920
7
AOP
6
5
AON
GNDB
VDDA
1
AIP
2
AIN
3
GNDA
4
NC
5
NC
6
NC
7
GNDA
8
16
GNDB
15
NC
14
VDDB
Si8920
13
AOP
12
NC
11
AON
10
NC
9
GNDB
Patents pending
Preliminary Rev. 0.5 8/15
Copyright © 2015 by Silicon Laboratories
Si8920
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si8920
2
Preliminary Rev. 0.5
Si8920
T
ABLE
Section
OF
C
ONTENTS
Page
1. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2.1. Regulatory Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3. Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5. Current Sense Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8. Package Outline: DIP8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
9. Land Pattern: DIP8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
10. Package Outline: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
11. Land Pattern: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
12. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
12.1. Si8920 Top Marking (DIP8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
12.2. Top Marking Explanation (DIP8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
12.3. Si8920 Top Marking (SOIC-16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
12.4. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Preliminary Rev. 0.5
3
Si8920
1. Functional Block Diagram
VDDA
AIP
AIN
GNDA
CMOS Isolation
UVLO
UVLO
VDDB
AOP
AON
GNDB
+
_
Mod
DeMod
+
_
Figure 1. Si8920 Block Diagram
4
Preliminary Rev. 0.5
Si8920
2. Electrical Specifications
Table 1. Electrical Specifications
V
DDA
, V
DDB
= 5 V, T
A
= –40 to +125 °C; typical specs at 25 °C
Parameter
Input Side Supply Voltage
Input Supply Current
Output Side Supply Voltage
Output Supply Current
VDD Undervoltage Threshold
VDD Undervoltage Threshold
VDD Undervoltage Hysteresis
Amplifier Bandwidth
Amplifier Input
Specified Full Scale
Input Amplitude
Si8920A
Si8920B
Symbol
VDDA
IVDDA
VDDB
IVDDB
VDDUV+
VDDUV–
VDD
HYS
Test Condition
V
AIP
= V
AIN
@ 3.3 V
V
AIP
= V
AIN
@ 3.3 V
VDDA, VDDB rising
VDDA, VDDB falling
Min
3.0
3.2
3.0
2.3
Typ
4.2
3.2
2.7
2.6
100
750
Max
5.5
5.5
5.5
4.1
Units
V
mA
V
mA
V
V
mV
kHz
VAIP – VAIN
VAIP – VAIN
VCM
VOS
VOS
T
–100
–200
±125
±250
–0.2
0.2
1.0
20
37.2
100
200
mV
mV
mV
mV
Maximum Input Volt- Si8920A
age Before Clipping Si8920B
Common-Mode Operating
Range
Input referred offset
Input offset drift
Differential Input
impedance
Amplifier Output
Full-scale Output
Gain
Gain Error
Gain Error Drift
Si8920A
Si8920B
Si8920A
Si8920B
1
1.5
V
mV
µV/°C
k
k
RIN
VAOP – VAON
1.58
1.62
16.2
8.1
1.65
Vpk
T
A
= 25 °C
–0.5
60
1.02
1.1
0.14
0.10
0.15
0.10
0.5
1.17
0.28
0.20
0.50
0.30
100
%
ppm/°C
V
mVrms
mVrms
%
%
k
pF
µs
Output Common Mode Voltage (VAOP + VAON)/2
Output Noise
Nonlinearity
Si8920A
Si8920B
Si8920A
Si8920B
Output Resistive Load
Output Capacitive Load
Timing
Signal Delay
RLOAD
CLOAD
tPD
50% to 50%
50% to 99%
10% to 90%
AIP = AIN = AGND,
VCM = 1500 V
100 kHz bandwidth
100 kHz bandwidth
5
0.75
1.85
0.42
50
75
Common-Mode Transient
Immunity*
CMTI
kV/µs
*Note:
An analog CMTI failure is defined as an output error of more than 100 mV persisting for at least 1 µs.
Preliminary Rev. 0.5
5
stm32/stm8
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