S i 8 7 1 x /2 x
5
K
V
L E D E
MU LAT OR
I
NPUT
, L
O G I C
O
UTPUT
I
SOLATORS
Wide range of product options
Inverting and non-inverting
Disable output high, low or tri-state
1 channel diode emulator input
Propagation delay 30 ns
Up to 5000 V
RMS
isolation
10 kV surge withstand capability
AEC-Q100 qualified
Wide operating temperature range
– 40 to +125 °C
RoHS-compliant packages
SOIC-8 (Narrow body)
DIP8 (Gull-wing)
SDIP6 (Stretched SO-6)
Features
High Speed: dc to 15 Mbps
2.5 to 5.5 V logic output
Pin-compatible, drop-in upgrades for
popular high-speed digital
optocouplers
Performance and reliability
advantages vs. optocouplers
Resistant to temperature, age and
forward current effects
10x lower FIT rate for longer
service life
Higher common-mode transient
immunity: >50 kV/µs typical
Lower power and forward input
diode current
Pin Assignments:
See page 21
NC
1
UVLO
8
VDD
ANODE
2
e
7
NC
CATHODE
3
6
VO
GND
NC
4
5
SOIC-8, DIP8
Industry Standard Pinout
NC
1
UVLO
Applications
Industrial automation
Isolated data acquisition
Motor controls and drives
Test and measurement equipment
Isolated switch mode power supplies
8
VDD
ANODE
2
e
7
EN
CATHODE
3
6
VO
GND
Safety Regulatory Approvals (Pending)
NC
4
5
UL 1577 recognized
Up
VDE certification conformity
IEC60747-5-2/VDE0884-10
CSA component notice 5A
approval
IEC
to 5000 Vrms for 1 minute
CQC certification approval
GB4943.1
(basic/reinforced insulation)
SOIC-8, DIP8 with Output Enable
Industry Standard Pinout
60950-1, 61010-1, 60601-1
(reinforced insulation)
ANODE 1
NC 2
e
6
UVLO
VDD
VO
Description
The Si871x/2x isolators are pin-compatible, single-channel, drop-in
replacements for popular optocouplers with data rates up to 15 Mbps.
These devices isolate high-speed digital signals and offer performance,
reliability, and flexibility advantages not available with optocoupler
solutions. The Si871x/2x series is based on Silicon Labs' proprietary
CMOS isolation technology for low-power and high-speed operation and
are resistant to the wear-out effects found in optocouplers that degrade
performance with increasing temperature, forward current, and device
age. As a result, the Si871x/2x series offer longer service life and
dramatically higher reliability compared to optocouplers. Ordering options
include logic output with and without output enable options.
5
CATHODE 3
4
GND
SDIP6
Industry Standard Pinout
Patent pending
Rev. 1.0 8/14
Copyright © 2014 by Silicon Laboratories
Si871x/2x
Si871x/2x
Functional Block Diagram
Diode
Emulator
VDD
A1
XMIT
I
F
REC
Output
Stage
(Logic Out)
OUT
C1
GND
2
Rev. 1.0
Si871x/2x
T
ABLE
Section
OF
C
ONTENTS
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3. Technical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.1. Device Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.2. Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3.3. Under Voltage Lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4. Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1. Input Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2. Output Circuit Design and Power Supply Connections . . . . . . . . . . . . . . . . . . . . . . . 18
5. Pin Descriptions (SOIC-8, DIP8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6. Pin Descriptions (SOIC-8, DIP8) with Output Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7. Pin Descriptions (SDIP6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
9. Package Outline: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
10. Land Pattern: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
11. Package Outline: DIP8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
12. Land Pattern: DIP8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
13. Package Outline: SDIP6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
14. Land Pattern: SDIP6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
15. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
15.1. Top Marking (8-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
15.2. Top Marking Explanation (8-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . 31
15.3. Top Marking (DIP8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
15.4. Top Marking Explanation (DIP8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
15.5. Top Marking (SDIP6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
15.6. Top Marking Explanation (SDIP6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Rev. 1.0
3
Si871x/2x
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
V
DD
Supply Voltage
Input Current
Operating Temperature (Ambient)
Symbol
V
DD
I
F(ON)
(See Figure 1)
T
A
Min
2.5
6
–40
Typ
—
—
—
Max
5.5
30
125
Unit
V
mA
°C
Table 2. Electrical Characteristics
Parameter
DC Parameters
Supply Voltage
Supply Current
Input Current Threshold
Input Current
Hysteresis
Input Forward Voltage
(OFF)
Input Forward Voltage
(ON)
Input Capacitance
V
DD
I
DD
I
F(TH)
I
HYS
Symbol
V
DD
= 5 V; GND = 0 V; T
A
= –40 to +125 °C; typical specs at 25 °C
Test Condition
(V
DD
–GND)
Output high or low
(V
DD
= 2.5 to 5.5 V)
Min
2.5
—
—
—
—
1.4
Typ
—
1.5
—
0.34
—
—
Max
5.5
—
3.6
—
1
2.8
Unit
V
mA
mA
mA
V
V
V
F(OFF)
Measured at ANODE with respect to
CATHODE.
V
F(ON)
C
I
Measured at ANODE with respect to
CATHODE.
f = 100 kHz,
V
F
= 0 V,
V
F
= 2 V
I
OL
= 4 mA
I
OH
= –4 mA
—
—
—
V
DD
- 0.4
—
V
DD
- 0.4
—
15
15
0.2
V
DD
-
0.2
50
—
—
0
–30
2.2
2
100
—
—
0.4
—
—
—
0.4
—
0
2.35
2.25
—
pF
pF
V
V
V
V
µA
µA
V
V
mV
Logic Low Output
Voltage
Logic High Output
Voltage
Output Impedance
Enable High Min
Enable Low Max
Enable High Current
Draw
Enable Low Current
Draw
UVLO Threshold +
UVLO Threshold –
UVLO lockout
hysteresis
V
OL
V
OH
Z
O
V
EH
V
EL
I
EH
I
EL
VDD
UV+
VDD
UV–
VDD
HYS
V
DD
= V
EH
= 5 V
V
DD
=5 V, V
EL
= 0 V
See Figure 8 on page 16.
V
DD
rising
See Figure 8 on page 16.
V
DD
falling
—
—
—
—
50
4
Rev. 1.0
Si871x/2x
Table 2. Electrical Characteristics (Continued)
Parameter
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
(Low-to-High)
Propagation Delay
(High-to-Low)
Pulse Width Distortion
Propagation Delay
Skew
Symbol
F
DATA
MPW
t
PLH
t
PHL
PWD
C
L
= 15 pF
C
L
= 15 pF
| t
PLH
– t
PHL
|
V
DD
= 5 V; GND = 0 V; T
A
= –40 to +125 °C; typical specs at 25 °C
Test Condition
Min
DC
66
5
5
—
—
Typ
—
—
—
—
—
—
Max
15
—
50
50
25
25
Unit
M
BPS
ns
ns
ns
ns
ns
AC Switching Parameters (V
DD
=5 V, C
L
= 15 pF)
t
PSK(p-p)
t
PSK(P-P)
is the magnitude of the dif-
ference in prop delays between dif-
ferent units operating at same supply
voltage, load, and ambient temp.
t
R
t
F
t
START
CMTI
Output = low or high
V
CM
=1500 V (See Figure 2)
I
F
= 6 mA
C
L
= 15 pF
C
L
= 15 pF
Rise Time*
Fall Time*
Device Startup Time
Common Mode
Transient Immunity
—
—
—
2.5
2.5
—
4
4
40
ns
ns
µs
35
50
—
kV/µs
*Note:
Guaranteed by design and/or characterization
Rev. 1.0
5
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