Si8650/51/52/55
L
O W
P
O W E R
F
I V E
- C
HANNEL
D
IGITAL
I
SOLATOR
Features
High-speed operation
DC to 150 Mbps
No start-up initialization required
Wide Operating Supply Voltage
2.5–5.5 V
Up to 5000 V
RMS
isolation
60-year life at rated working voltage
High electromagnetic immunity
Ultra low power (typical)
5 V Operation
1.6 mA per channel at 1 Mbps
5.5 mA per channel at 100 Mbps
2.5 V Operation
1.5 mA per channel at 1 Mbps
3.5 mA per channel at 100 Mbps
Tri-state outputs with ENABLE
Schmitt trigger inputs
Selectable fail-safe mode
Default high or low output
(ordering option)
Precise timing (typical)
10 ns propagation delay
1.5 ns pulse width distortion
0.5 ns channel-channel skew
2 ns propagation delay skew
5 ns minimum pulse width
Transient Immunity 50 kV/µs
AEC-Q100 qualification
Wide temperature range
–40 to 125 °C
RoHS-compliant packages
SOIC-16 wide body
SOIC-16 narrow body
QSOP-16
Applications
Industrial automation systems
Medical electronics
Hybrid electric vehicles
Isolated switch mode supplies
Isolated ADC, DAC
Motor control
Power inverters
Communication systems
Safety Regulatory Approvals
UL 1577 recognized
Up to 5000 V
RMS
for 1 minute
CSA component notice 5A approval
IEC 60950-1, 61010-1, 60601-1
(reinforced
insulation)
VDE certification conformity
IEC 60747-5-2
(VDE0884 Part 2)
EN60950-1
(reinforced insulation)
Ordering Information:
See page 30.
CQC certification approval
GB4943.1
Description
Silicon Lab's family of ultra-low-power digital isolators are CMOS devices
offering substantial data rate, propagation delay, power, size, reliability, and
external BOM advantages over legacy isolation technologies. The operating
parameters of these products remain stable across wide temperature ranges
and throughout device service life for ease of design and highly uniform
performance. All device versions have Schmitt trigger inputs for high noise
immunity and only require VDD bypass capacitors.
Data rates up to 150 Mbps are supported, and all devices achieve propagation
delays of less than 10 ns. Enable inputs provide a single point control for
enabling and disabling output drive. Ordering options include a choice of
isolation ratings (2.5, 3.75 and 5 kV) and a selectable fail-safe operating mode
to control the default output state during power loss. All products >1 kV
RMS
are
safety certified by UL, CSA, VDE, and CQC, and products in wide-body
packages support reinforced insulation withstanding up to 5 kV
RMS
.
Rev. 1.8 6/15
Copyright © 2015 by Silicon Laboratories
Si8650/51/52/55
Si8650/51/52/55
2
Rev. 1.8
Si8650/51/52/55
T
ABLE
Section
OF
C
ONTENTS
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2. Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1. Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
3.2. Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.3. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.4. Fail-Safe Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.5. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4. Pin Descriptions (Si8650/51/52) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5. Pin Descriptions (Si8655) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7. Package Outline: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8. Land Pattern: 16-Pin Wide-Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9. Package Outline: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10. Land Pattern: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
11. Package Outline: 16-Pin QSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
12. Land Pattern: 16-Pin QSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
13. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
13.1. Top Marking (16-Pin Wide Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
13.2. Top Marking Explanation (16-Pin Wide Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . 40
13.3. Top Marking (16-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
13.4. Top Marking Explanation (16-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . 41
13.5. Top Marking (16-Pin QSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
13.6. Top Marking Explanation (16-Pin QSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Rev. 1.8
3
Si8650/51/52/55
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Operating Temperature*
Supply Voltage
Symbol
T
A
V
DD1
V
DD2
Min
–40
2.5
2.5
Typ
25
—
—
Max
125
5.5
5.5
Unit
ºC
V
V
*Note:
The maximum ambient temperature is dependent on data frequency, output loading, number of operating channels,
and supply voltage.
Table 2. Electrical Characteristics
(V
DD1
= 5 V±10%, V
DD2
= 5 V±10%, T
A
= –40 to 125 °C)
Parameter
VDD Undervoltage
Threshold
VDD Undervoltage
Threshold
VDD Undervoltage
Hysteresis
Positive-Going Input
Threshold
Negative-Going
Input Threshold
Input Hysteresis
High Level Input Voltage
Low Level input voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Output Impedance
1
Enable Input High Current
Enable Input Low Current
Symbol
VDDUV+
VDDUV–
VDD
HYS
VT+
VT–
V
HYS
V
IH
V
IL
V
OH
V
OL
I
L
Z
O
I
ENH
I
ENL
Test Condition
V
DD1
, V
DD2
rising
V
DD1
, V
DD2
falling
Min
1.95
1.88
50
Typ
2.24
2.16
70
1.67
1.23
0.44
—
—
4.8
0.2
—
50
2.0
2.0
Max
2.375
2.325
95
1.9
1.4
0.50
—
0.8
—
0.4
±10
—
—
—
Unit
V
V
mV
V
V
V
V
V
V
V
µA
µA
µA
All inputs rising
All inputs falling
1.4
1.0
0.38
2.0
—
loh = –4 mA
lol = 4 mA
V
DD1
,V
DD2
– 0.4
—
—
—
V
ENx
= V
IH
V
ENx
= V
IL
—
—
Notes:
1.
The nominal output impedance of an isolator driver channel is approximately 50
,
±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2.
t
PSK(P-P)
is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3.
Start-up time is the time period from the application of power to valid data at the output.
4
Rev. 1.8
Si8650/51/52/55
Table 2. Electrical Characteristics (Continued)
(V
DD1
= 5 V±10%, V
DD2
= 5 V±10%, T
A
= –40 to 125 °C)
Parameter
Si8650Bx, Ex, Si8655Bx
V
DD1
V
DD2
V
DD1
V
DD2
Si8651Bx, Ex
V
DD1
V
DD2
V
DD1
V
DD2
Si8652Bx, Ex
V
DD1
V
DD2
V
DD1
V
DD2
Si8650Bx, Ex, Si8655Bx
V
DD1
V
DD2
Si8651Bx, Ex
V
DD1
V
DD2
Si8652Bx, Ex
V
DD1
V
DD2
Si8650Bx, Ex, Si8655Bx
V
DD1
V
DD2
Si8651Bx, Ex
V
DD1
V
DD2
Si8652Bx, Ex
V
DD1
V
DD2
Symbol
Test Condition
Min
Typ
Max
Unit
DC Supply Current
(All inputs 0 V or at Supply)
V
I
= 0(Bx), 1(Ex)
V
I
= 0(Bx), 1(Ex)
V
I
= 1(Bx), 0(Ex)
V
I
= 1(Bx), 0(Ex)
V
I
= 0(Bx), 1(Ex)
V
I
= 0(Bx), 1(Ex)
V
I
= 1(Bx), 0(Ex)
V
I
= 1(Bx), 0(Ex)
V
I
= 0(Bx), 1(Ex)
V
I
= 0(Bx), 1(Ex)
V
I
= 1(Bx), 0(Ex)
V
I
= 1(Bx), 0(Ex)
—
—
—
—
—
—
—
—
—
—
—
—
1.1
3.1
7.0
3.3
1.5
2.7
6.6
4.0
2.0
2.4
5.6
5.0
1.8
4.7
9.8
5.0
2.4
4.1
9.2
6.0
3.0
3.6
7.8
7.5
mA
mA
mA
1 Mbps Supply Current
(All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
—
—
—
—
—
—
4.1
3.7
4.2
3.8
4.0
4.0
5.7
5.2
5.8
5.3
5.6
5.6
mA
mA
mA
10 Mbps Supply Current
(All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
—
—
—
—
—
—
4.1
5.2
4.4
4.9
4.6
4.9
5.7
7.2
6.2
6.9
6.4
6.8
mA
mA
mA
Notes:
1.
The nominal output impedance of an isolator driver channel is approximately 50
,
±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2.
t
PSK(P-P)
is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3.
Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.8
5
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