Si5369
A
N Y
- F
REQUENCY
P
RECISION
C
L O C K
M
ULTIPLIER
/J
I T T E R
A
TTENUATOR
Features
Generates any frequency from 2 kHz
to 945 MHz and select frequencies to
1.4 GHz from an input frequency of
2 kHz to 710 MHz
Ultra-low jitter clock outputs with jitter
generation as low as 300 fs rms
(12 kHz–20 MHz)
Integrated loop filter with selectable
loop bandwidth (4 Hz to 525 Hz)
Meets OC-192 GR-253-CORE jitter
specifications
Four clock inputs with manual or
automatically controlled hitless
switching and phase build-out
Supports holdover and freerun
modes of operation
SONET frame sync switching and
regeneration
Five clock outputs with selectable
signal format (LVPECL, LVDS, CML,
CMOS)
Support for ITU G.709 and custom
FEC ratios (253/226, 239/237,
255/238, 255/237, 255/236)
LOL, LOS, FOS alarm outputs
Digitally-controlled output phase
adjust
I
2
C or SPI programmable settings
On-chip voltage regulator for 1.8 V
±5%, 2.5 V ±10%, or 3.3 V ±10%
operation
Small size: 14 x 14 mm 100-pin
TQFP
Pb-free, RoHS compliant
Ordering Information:
See page 78.
Applications
SONET/SDH OC-48/STM-16/OC-
192/STM-64 line cards
GbE/10GbE, 1/2/4/8/10G FC line cards
ITU G.709 and custom FEC line cards
Wireless repeaters/wireless backhaul
Data converter clocking
OTN/WDM Muxponder, MSPP,
ROADM line cards
SONET/SDH + PDH clock
synthesis
Test and measurement
Synchronous Ethernet
Broadcast video
Description
The Si5369 is a jitter-attenuating precision clock multiplier for applications
requiring sub 1 ps rms jitter performance. The Si5369 accepts four clock inputs
ranging from 2 kHz to 710 MHz and generates five clock outputs ranging from
2 kHz to 945 MHz and select frequencies to 1.4 GHz. The device provides
virtually any frequency translation combination across this operating range. The
outputs are divided down separately from a common source. The Si5369 input
clock frequency and clock multiplication ratio are programmable through an I
2
C or
SPI interface. The Si5369 is based on Silicon Laboratories' third-generation
DSPLL
®
technology, which provides any-frequency synthesis and jitter
attenuation in a highly integrated PLL solution that eliminates the need for
external VCXO and loop filter components. The DSPLL loop bandwidth is digitally
programmable, providing jitter performance optimization at the application level.
Operating from a single 1.8, 2.5 ,or 3.3 V supply, the Si5369 is ideal for providing
clock multiplication and jitter attenuation in high performance timing applications.
Rev. 1.0 1/13
Copyright © 2013 by Silicon Laboratories
Si5369
Si5369
T
ABLE
Section
OF
C
ONTENTS
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Phase Noise Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1. External Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2. Further Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5. Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
6. Pin Descriptions: Si5369 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
8. Package Outline: 100-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
9. Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
10. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Rev. 1.0
3
Si5369
1. Electrical Specifications
Table 1. Recommended Operating Conditions
1
Parameter
Ambient Temperature
Supply Voltage during
Normal Operation
Symbol
T
A
V
DD
3.3 V Nominal
2
2.5 V Nominal
1.8 V Nominal
Test Condition
Min
-40
2.97
2.25
1.71
Typ
25
3.3
2.5
1.8
Max
85
3.63
2.75
1.89
Unit
C
V
V
V
Notes:
1.
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 ºC unless otherwise stated.
2.
The LVPECL and CMOS output formats draw more current than either LVDS or CML; however, there are restrictions in
the allowed output format pin settings so that the maximum power dissipation for the TQFP devices is limited when
they are operated at 3.3 V. When there are four enabled LVPECL or CMOS outputs, the fifth output must be disabled.
When there are five enabled outputs, there can be no more than three outputs that are either LVPECL or CMOS.
SIGNAL +
Differential I/Os V , V
OCM
ICM
SIGNAL –
V
V
ISE
, V
OSE
Single-Ended
Peak-to-Peak Voltage
(SIGNAL +) – (SIGNAL –)
V
ID
,V
OD
V
ICM
, V
OCM
t
Differential Peak-to-Peak Voltage
SIGNAL +
V
ID
= (SIGNAL+) – (SIGNAL–)
SIGNAL –
Figure 1. Differential Voltage Characteristics
80%
CKIN, CKOUT
20%
t
F
t
R
Figure 2. Rise/Fall Time Characteristics
4
Rev. 1.0
Si5369
Table 2. DC Characteristics
(V
DD
= 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, T
A
= –40 to 85 °C)
Parameter
Supply Current
1,6
Symbol
I
DD
Test Condition
LVPECL Format
622.08 MHz Out
All CKOUTs Enabled
LVPECL Format
622.08 MHz Out
1 CKOUT Enabled
CMOS Format
19.44 MHz Out
All CKOUTs Enabled
CMOS Format
19.44 MHz Out
1 CKOUT Enabled
Disable Mode
Min
—
Typ
394
Max
435
Unit
mA
—
253
284
mA
—
278
400
mA
—
229
261
mA
—
165
—
mA
CKINn Input Pins
2
Input Common Mode
Voltage (Input Thresh-
old Voltage)
V
ICM
1.8 V ± 5%
2.5 V ± 10%
3.3 V ± 10%
Input Resistance
Single-Ended Input
Voltage Swing
(See Absolute Specs)
CKN
RIN
V
ISE
Single-ended
f
CKIN
< 212.5 MHz
See Figure 1.
f
CKIN
> 212.5 MHz
See Figure 1.
V
ID
f
CKIN
< 212.5 MHz
See Figure 1.
fCKIN > 212.5 MHz
See Figure 1.
0.9
1
1.1
20
0.2
0.25
0.2
0.25
—
—
—
40
—
—
—
—
1.4
1.7
1.95
60
—
—
—
—
V
V
V
k
V
PP
V
PP
V
PP
V
PP
Differential Input
Voltage Swing
(See Absolute Specs)
Notes:
1.
Current draw is independent of supply voltage
2.
No under- or overshoot is allowed.
3.
LVPECL outputs require nominal VDD
≥
2.5 V.
4.
This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family
Reference Manual for more details.
5.
LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.
6.
The LVPECL and CMOS output formats draw more current than either LVDS or CML; however, there are restrictions in
the allowed output format pin settings so that the maximum power dissipation for the TQFP devices is limited when
they are operated at 3.3 V. When there are four enabled LVPECL or CMOS outputs, the fifth output must be disabled.
When there are five enabled outputs, there can be no more than three outputs that are either LVPECL or CMOS.
Rev. 1.0
5
stm32/stm8
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