S i5345/44/4 2
10 -C
H A N N E L
, A
N Y
- F
R E Q U E N C Y
, A
N Y
-O
U T P U T
J
I T T E R
A
T T E N U A T O R
/ C
L O C K
M
U L T I P L I E R
Features
Generates any combination of output
Optional zero delay mode
frequencies from any input frequency
Fastlock feature for low nominal
Input frequency range:
bandwidths
Differential: 8 kHz to 750 MHz
Glitchless on the fly output frequency
LVCMOS: 8 kHz to 250 MHz
changes
Output frequency range:
DCO mode: as low as 0.001 ppb steps.
Differential: up to 712.5 MHz
Core voltage
LVCMOS: up to 250 MHz
V
DD
: 1.8 V ±5%
Ultra-low jitter:
V
DDA
: 3.3 V ±5%
<100 fs typ (12 kHz–20 MHz)
Independent output clock supply pins:
Programmable jitter attenuation
3.3 V, 2.5 V, or 1.8 V
bandwidth from 0.1 Hz to 4 kHz
Output-output skew: 20 ps typ
Meets G.8262 EEC Opt 1, 2 (SyncE)
Serial interface: I
2
C or SPI
Highly configurable outputs compatible
In-circuit programmable with
with LVDS, LVPECL, LVCMOS, CML,
non-volatile OTP memory
and HCSL with programmable signal
ClockBuilder Pro
TM
software simplifies
amplitude
device configuration
Status monitoring (LOS, OOF, LOL)
Hitless input clock switching: automatic
Si5345: 4 input, 10 output, 64 QFN
Si5344: 4 input, 4 output, 44 QFN
or manual
Si5342: 4 input, 2 output, 44 QFN
Locks to gapped clock inputs
Temperature range: –40 to +85 °C
Automatic free-run and holdover
Pb-free, RoHS-6 compliant
modes
Ordering Information:
See section 8
Functional Block Diagram
Device Selector Guide
Grade
Si534fA
Si534fB
Si534fC
Si534fD
Max Output Frequency
712.5 MHz
350 MHz
712.5 MHz
350 MHz
Frequency Synthesis Modes
Integer+Fractional
Integer+Fractional
Integer
Integer
Applications
OTN Muxponders and Transponders
10/40/100G networking line cards
GbE/10GbE/100GbE Synchronous
Ethernet (ITU-T G.8262)
Carrier Ethernet switches
SONET/SDH Line Cards
Broadcast video
Test and measurement
ITU-T G.8262 (SyncE) Compliant
Description
These jitter attenuating clock multipliers combine fourth-generation DSPLL and
MultiSynth™ technologies to enable any-frequency clock generation and jitter
attenuation for applications requiring the highest level of jitter performance. These
devices are programmable via a serial interface with in-circuit programmable non-
volatile memory (NVM) so they always power up with a known frequency configuration.
They support free-run, synchronous, and holdover modes of operation, and offer both
automatic and manual input clock switching. The loop filter is fully integrated on-chip,
eliminating the risk of noise coupling associated with discrete solutions. Further, the
jitter attenuation bandwidth is digitally programmable, providing jitter performance
optimization at the application level. Programming the Si5345/44/42 is easy with Silicon
Labs’
ClockBuilder Pro
software. Factory preprogrammed devices are also available.
Rev. 1.0 7/15
Copyright © 2015 by Silicon Laboratories
Si5345/44/42
Si5345/ 44/42
T
A B L E
O
F
C
O N T E N T S
1. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
3. Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4. Detailed Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
5. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
5.1. Frequency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
5.2. DSPLL Loop Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
5.3. Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
5.4. External Reference (XA/XB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
5.5. Digitally Controlled Oscillator (DCO) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
5.6. Inputs (IN0, IN1, IN2, IN3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
5.7. Fault Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
5.8. Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
5.9. Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
5.10. In-Circuit Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
5.11. Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
5.12. Custom Factory Preprogrammed Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
5.13. Enabling Features and/or Configuration Settings Unavailable in
ClockBuilder Pro for Factory Preprogrammed Devices . . . . . . . . . . . . . . . . . . . . . .43
6. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
6.1. Addressing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
6.2. High-Level Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
7. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
8.1. Ordering Part Number Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
9. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
9.1. Si5345 9x9 mm 64-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
9.2. Si5344 and Si5342 7x7 mm 44-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . .57
10. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
11. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
12. Device Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
2
Rev. 1.0
Si5345/4 4/42
1. Typical Application Schematic
Figure 1. 10G Ethernet Data Center Switch and Compute Blade Schematic
Rev. 1.0
3
Si5345/ 44/42
2. Electrical Specifications
Table 1. Recommended Operating Conditions*
(V
DD
= 1.8 V ±5%, V
DDA
= 3.3 V ±5%,T
A
= –40 to 85 °C)
Parameter
Ambient Temperature
Junction Temperature
Core Supply Voltage
Symbol
T
A
TJ
MAX
V
DD
V
DDA
V
DDO
Min
–40
—
1.71
3.14
3.14
2.38
1.71
Typ
25
—
1.80
3.30
3.30
2.50
1.80
3.30
1.80
Max
85
125
1.89
3.47
3.47
2.62
1.89
3.47
1.89
Unit
°C
°C
V
V
V
V
V
V
V
Clock Output Driver Supply Voltage
Status Pin Supply Voltage
V
DDS
3.14
1.71
*Note:
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.
4
Rev. 1.0
Si5345/4 4/42
Table 2. DC Characteristics
(V
DD
= 1.8 V ±5%, V
DDA
= 3.3 V ±5%, V
DDO
= 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, T
A
= –40 to 85 °C)
Parameter
Core Supply Current
Symbol
I
DD
Test Condition
Si5345
Si5344
Si5342
Min
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Typ
125
105
105
120
115
115
21
15
21
16
12
880
720
715
Max
185
155
155
125
120
120
25
18
25
18
13
1040
850
840
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mW
mW
mW
I
DDA
Si5345
Si5344
Si5342
LVPECL Output
4
@ 156.25 MHz
LVDS Output
4
@ 156.25 MHz
3.3 V LVCMOS
5
output
@ 156.25 MHz
2.5 V LVCMOS
5
output
@ 156.25 MHz
1.8 V LVCMOS
5
output
@ 156.25 MHz
Output Buffer Supply Current
I
DDOx
Total Power Dissipation
P
d
Si5345
Si5344
Si5342
Notes 1, 6
Notes 2, 6
Notes 3, 6
Notes:
1.
Si5345 test configuration: 10x 3.3 V LVDS outputs enabled @156.25 MHz. Excludes power in termination resistors.
2.
Si5344 test configuration: 4x 3.3 V LVDS outputs enabled @ 156.25 MHz. Excludes power in termination resistors.
3.
Si5342 test configuration: 2x 3.3 V LVDS outputs enabled @ 156.25 MHz. Excludes power in termination resistors.
4.
Differential outputs terminated into an AC coupled 100
load.
5.
LVCMOS outputs measured into a 6 inch 50
PCB trace with 5 pF load. Measurements were made in CMOS3 mode.
6.
Detailed power consumption for any configuration can be estimated using
ClockBuilder Pro
when an evaluation board
(EVB) is not available. All EVBs support detailed current measurements for any configuration.
Rev. 1.0
5
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
