S i886xxISO- EVB
Si886
X X
ISO - EVB U
S E R
’
S
G
U I D E
Description
This document describes
Si886xxISO-EVB.
the
operation
of
the
Si886xxISO-EVB Overview
Kit Contents
The Si886xxISO Evaluation Kit contains the following
items:
Si886xxISO-EVB
Si88621ED-IS installed on the evaluation board.
Rev. 0.1
Copyright © 2015 by Silicon Laboratories
Si886xxISO-EVB
Si886xxISO - EVB
1. Hardware Overview and Setup
The default configuration of the Si886xxISO-EVB demonstrates the digital isolation capabilities of the installed
Si88621ED-IS as well as its dc-dc converter performance. In this configuration, the dc-dc converter is enabled, the
primary side digital supply is sourced by an external regulator circuit, and the secondary side digital supply is
sourced by the output of the converter. This EVB configuration has a jumper installed at JP9 in the ON position,
JP13 has a jumper installed, and the remaining jumpers not populated.
Note:
Do not place jumpers across JP10 or JP11. These are additional test points for VDDA, GNDA and GNDB, and VOUT
respectively.
1.1. DC-DC Converter Input and Output
Supply power to the EVB by applying 24 Vdc to VIN at terminal block J1. LED D21 above terminal block J1
illuminates to show power applied to primary side of the converter.
The isolated dc-dc output, VOUT, is available at terminal block J2. The populated values for R5 and R6 produce a
5 V output at VOUT capable of sourcing up to 5 W to an external load connected to terminal block J2. LED D22
above the terminal block J2 illuminates when the dc-dc converter is operating.
VIN and VOUT test points are available along the upper edge of the EVB.
1.2. Digital Isolator Supplies
The A-side power is provided by a regulator circuit referenced to VREGA pin of the Si888621ED-IS. VIN is stepped
down from 24 V to approximately 4.3 V and applied to VDDA pin.
The B-side power is supplied by the output of the dc-dc converter through JP13.
1.3. Digital Signals
The EVB has a series of header pins for connecting to each digital channel. The inside conductor of each 2x1
header is connected to the device pin and the outer conductor is tied to ground through a resistor of 499
.
Connect digital signals to each side of the Si886xxISO-EVB through a two-row ribbon cable with one row
grounded.
1 transmits from A1 (JP1 pin 2) to B1 (JP4 pin 1).
Channel 2 transmits from B2 (JP5 pin 1) to A2 (JP2 pin 2).
Note:
The digital input signal should not exceed the power supply of the respective side.
Channel
1.4. Transformer Current Sensing
Primary side magnetizing current across the sense resistor R12, can be observed by probing TP20, RSNS with
reference to TP33, GNDP.
2
Rev. 0.1
Si886xx ISO-E VB
2. Alternative Configurations
2.1. Disabling the DC-DC Converter
The SH_FC input (U1 pin 7) disables the dc-dc converter. JP9 controls the SH_FC input, enabling the converter
when pulled low, ON, and disabling the converter when pulled high, OFF. To disable the dc-dc converter, place the
jumper in the OFF position on JP9.
If interfacing to an external controller through the JP9 header, the controller must drive SH low for normal operation
and high to disable the dc-dc.
Note:
When the dc-dc converter is disabled, the B-side can be powered by an active high digital input on the B-side. Ensure B2
input is tri-state or driven low when VDDB is left floating or grounded.
2.2. 3.3 V DC-DC Converter Output
To change VOUT to 3.3 V, change R5 to 43.2 k and R6 to 20.0 k.
2.3. Alternate Supply for VDDA
To bypass the regulator circuit and supply VDDA from a separate supply, remove Q2 and connect positive power
supply through JP9 pin 3 and connect the supply return to J1 pin 2.
2.4. Alternate Supply for VDDB
To supply VDDB from a separate supply, remove the jumper on JP13 and supply desired power through JP13 pin 2
and connect the supply return to J2 pin 1.
Rev. 0.1
3
Si886xxISO - EVB
3. Quick Reference Tables
Table 1. Test Point Descriptions
Test Point
TP1
TP2
TP3
TP4
TP5
TP19
TP20
TP33
Description
VIN
GNDA/GNDP
VOUT
GNDB
SHDN
COMP
RSNS
GNDP
Referenced to
GNDA/GNDP
N/A
GNDB
N/A
GNDA/GNDP
GNDB
GNDA/GNDP
N/A
Table 2. Jumper Descriptions
Jumper
JP1
JP2
JP5
JP6
JP9
JP10
JP11
JP13
PIN 1*
GNDA
(through 499
)
GNDA
(through 499
)
B1
B2
GNDA
VIN
GNDB
VDDB
PIN 2*
A1
A2
GNDB
(through 499
)
GNDB
(through 499
)
SHDN
GNDA
VOUT
VOUT
PIN 3*
—
—
—
—
VDDA
—
—
—
Default Position
Not Installed
Not Installed
Not Installed
Not Installed
Installed
(SHDN - GNDA)
Not Installed
Not Installed
Installed
Description
Digital Isolator Connector
Digital Isolator Connector
Digital Isolator Connector
Digital Isolator Connector
DC-DC Converter Enabled
DO NOT SHORT –
test points only
DO NOT SHORT –
test points only
Connects VDDB to VOUT
*Note:
Pin numbering is from left to right.
4
Rev. 0.1
VOUT
VIN
*2
J2
2
1
D22
RED
D21
RED
R22
10K
R21
69.8K
J1
*1
1
2
D20
28V
VIN
TP2
GNDA
TP1
VIN
TP3
VOUT
TP4
GNDB
VOUT
This is an OUTPUT
DO NOT connect an external power supply to J2
Input Power Supply
U1
VIN
VOUT
JP10
JP11
Valid range: 24V +/- 10%
R24
A1
499
R25
A2
499
499
B2
JP2
JP6
R29
499
B1
4. Si886xxISO-EVB Schematics
JP1
JP5
R28
VDDA
JP9
TP5
SHDN
GNDA
GNDB
1
2
3
JS9
HEADER 1x3
Si88621
SH
Rev. 0.1
Si886xx ISO-E VB
Figure 1. Si886xxISO-EVB Schematic (1 of 2)
5
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