Si53308
D
U A L
1 : 3 L
O W
- J
I T T E R
B
UFFER
/ L
EVEL
T
RANSLATOR
Features
6 differential or 12 (in phase)
LVCMOS outputs
Ultra-low additive jitter: 45 fs rms
Wide frequency range: 1 to 725 MHz
Any-format input with pin selectable
output formats: LVPECL, low power
LVPECL, LVDS, CML, HCSL,
LVCMOS
Synchronous output enable
Output clock division: /1, /2, /4
Low output-output skew: 25 ps
Loss of signal (LOS) monitors for
loss of input clock
Independent V
DD
and V
DDO
:
1.8/2.5/3.3 V
Selectable LVCMOS drive strength to
tailor jitter and EMI performance
Small size: 32-QFN (5 mm x 5 mm)
RoHS compliant, Pb-free
Industrial temperature range:
–40 to +85 °C
Applications
Ordering Information:
See page 28.
Storage
Telecom
Industrial
Servers
Backplane clock distribution
Q2
Q3
29
28
Description
The Si53308 is an ultra low jitter six output differential buffer with pin-selectable
output clock signal format and divider selection. The device is a dual 1:3 buffer
providing the functionality of two independent buffers in a single IC. The Si53308
utilizes Silicon Laboratories' advanced CMOS technology to fanout clocks from 1
to 725 MHz with guaranteed low additive jitter, low skew, and low propagation
delay variability. The Si53308 features minimal cross-talk and provides superior
supply noise rejection, simplifying low jitter clock distribution in noisy
environments. Independent core and output bank supply pins provide integrated
level translation without the need for external circuitry.
DIVA
SFOUTA[1]
SFOUTA[0]
Q0
Q0
GND
V
DD
NC
Q4
Q4
26
25
Q1
Q1
Q2
Q3
27
High-speed clock distribution
Ethernet switch/router
Optical Transport Network (OTN)
SONET/SDH
PCI Express Gen 1/2/3
Pin Assignments
Si53308
32
31
30
1
2
3
4
5
6
7
8
12
13
10
14
11
15
16
24
23
22
DIVB
SFOUTB[1]
SFOUTB[0]
Q5
Q5
VDDOB
VDDOA
V
REF
GND
PAD
21
20
19
18
17
9
Functional Block Diagram
Patents pending
V
REF
Vref
Generator
Power
Supply
Filtering
DIV
A
V
DDOA
SFOUT
A
[1:0]
OE
A
Q0, Q1, Q2
DivA
Q0, Q1, Q2
CLK0
CLK0
DIV
B
V
DDOB
SFOUT
B
[1:0]
OE
B
CLK1
DivB
CLK1
Q3, Q4, Q5
Q3, Q4, Q5
Rev. 0.9 6/13
Copyright © 2013 by Silicon Laboratories
CLK1
LOS0
CLK0
CLK0
LOS1
OEA
OEB
CLK1
Si53308
Si53308
T
ABLE
Section
OF
C
ONTENTS
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1. Universal, Any-Format Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2. Input Bias Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3. Universal, Any-Format Output Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.4. Synchronous Output Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.5. Flexible Output Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.6. Output Enable Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.7. Loss of Signal (LOS) Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.8. Power Supply (V
DD
and V
DDOX
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.9. Output Clock Termination Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.10. AC Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.11. Typical Phase Noise Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.12. Input Noise Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.13. Power Supply Noise Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3. Pin Description: 32-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.1. 5x5 mm 32-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
6.1. 5x5 mm 32-QFN Package Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.1. Si53308 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Rev. 0.9
3
Si53308
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Operating
Temperature
Supply Voltage Range*
Symbol
T
A
V
DD
LVDS, CML
Test Condition
Min
–40
1.71
2.38
2.97
LVPECL, low power LVPECL,
LVCMOS
HCSL
Output Buffer Supply
Voltage*
V
DDOX
LVDS, CML
2.38
2.97
2.97
1.71
2.38
2.97
LVPECL, low power LVPECL,
LVCMOS
HCSL
*Note:
Core supply V
DD
and output buffer supplies V
DDO
are independent.
Typ
—
1.8
2.5
3.3
2.5
3.3
3.3
1.8
2.5
3.3
2.5
3.3
3.3
Max
85
1.89
2.63
3.63
2.63
3.63
3.63
1.89
2.63
3.63
2.63
3.63
3.63
Unit
°C
V
V
V
V
V
V
V
V
V
V
V
V
2.38
2.97
2.97
Table 2. Input Clock Specifications
(V
DD
=1.8 V
5%, 2.5 V
5%, or 3.3 V
10%, T
A
=–40 to 85 °C)
Parameter
Differential Input Com-
mon Mode Voltage
Differential Input Swing
(peak-to-peak)
LVCMOS Input High Volt-
age
LVCMOS Input Low Volt-
age
Input Capacitance
Symbol
V
CM
V
IN
V
IH
V
IL
C
IN
V
DD
= 2.5 V
5%, 3.3 V
10%
V
DD
= 2.5 V
5%, 3.3 V
10%
CLK0 and CLK1 pins with
respect to GND
Test Condition
V
DD
= 2.5 V
5%, 3.3 V
10%
Min
0.05
0.2
V
DD
x 0.7
—
—
Typ
—
—
—
—
5
Max
—
2.2
—
V
DD
x 0.3
—
Unit
V
V
V
V
pF
4
Rev. 0.9
Si53308
Table 3. DC Common Characteristics
(V
DD
= 1.8 V
5%,
2.5 V
5%, or 3.3 V
10%,T
A
= –40 to 85 °C)
Parameter
Supply Current
Output Buffer
Supply Current
(Per Clock Output)
@100 MHz (diff)
@200 MHz (CMOS)
Symbol
I
DD
I
DDOX
Test Condition
Min
—
Typ
65
35
35
20
35
35
8
15
VDD/2
—
Max
100
—
—
—
—
—
—
—
—
—
Unit
mA
mA
mA
mA
mA
mA
mA
mA
V
V
V
V
V
V
k
k
LVPECL (3.3 V)
Low Power LVPECL (3.3 V)*
LVDS (3.3 V)
CML (3.3 V)
HCSL, 100 MHz, 2 pF load
(3.3 V)
CMOS (2.5 V, SFOUT = Open/0),
per output, C
L
= 5 pF, 200 MHz
CMOS (3.3 V, SFOUT = 0/1),
per output, C
L
= 5 pF, 200 MHz
—
—
—
—
—
—
—
—
0.8xVDD
Voltage Reference
Input High Voltage
Input Mid Voltage
Input Low Voltage
Output Voltage High
Output Voltage Low
Internal Pull-down
Resistor
Internal Pull-up
Resistor
V
REF
V
IH
V
IM
V
IL
V
OH
V
OL
R
DOWN
R
UP
V
REF
pin (VDD = 2.5/3.3 V)
SFOUTX, DIVX, OEX
SFOUTX, DIVX
3-level input pins
SFOUTX, DIVX, OEX
I
DD
= –1 mA
I
DD
= 1 mA
DIVX, SFOUTX
DIVX, SFOUTX, OEX
0.45xVDD 0.5xVDD 0.55xVDD
—
0.8xVDD
—
—
—
—
—
—
25
25
0.2xVDD
—
0.2xVDD
—
—
*Note:
Low-power LVPECL mode supports an output termination scheme that will reduce overall system power.
Rev. 0.9
5
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