S i 5 3 115
15-O
UTPUT
PCI
E
G
EN
3
Features
BUFFER
/
Z
ERO
D
ELAY
B
UFFER
Fifteen 0.7 V low-power, push-
pull HCSL PCIe Gen3 outputs
100 MHz /133 MHz PLL
operation, supports PCIe and
QPI
PLL bandwidth SW SMBUS
programming overrides the latch
value from HW pin
9 selectable SMBUS addresses
SMBus address configurable to
allow multiple buffers in a single
control network 3.3 V supply
voltage operation
Separate VDDIO for outputs
PLL or bypass mode
Spread spectrum tolerable
1.05 to 3.3 V I/O supply voltage
50 ps output-to-output skew
50 ps cyc-cyc jitter (PLL mode)
Low phase jitter (Intel QPI, PCIe
Gen 1/2/3/4 common clock
compliant)
Gen 3 SRNS Compliant
100 ps input-to-output delay
Extended Temperature:
–40 to 85 °C
64-pin QFN
Ordering Information:
See page 30.
Pin Assignments
VDD_IO
DIF_14
DIF_14
VDD
GND
GND
DIF_12
DIF_12
DIF_11
DIF_11
DIF_13
DIF_13
GND
VDD_IO
DIF_10
DIF_10
Applications
Server
Storage
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
Data center
Enterprise switches and routers
Description
The Si53115 is a 15-output, low-power HCSL differential clock buffer that
meets all of the performance requirements of the Intel DB1200ZL
specification. The device is optimized for distributing reference clocks for
Intel
®
QuickPath Interconnect (Intel QPI), PCIe Gen 1/Gen 2/Gen 3/
Gen 4, SAS, SATA, and Intel Scalable Memory Interconnect (Intel SMI)
applications. The VCO of the device is optimized to support 100 MHz and
133 MHz operation. Each differential output can be enabled through I
2
C
for maximum flexibility and power savings. Measuring PCIe clock jitter is
quick and easy with the Silicon Labs PCIe Clock Jitter Tool. Download it
for free at
www.silabs.com/pcie-learningcenter.
VDDA
GNDA
100M_133M
HBW_BYPASS_LBW
PWRGD / PWRDN
GND
VDDR
CLK_IN
CLK_IN
SA_0
SDA
SCL
SA_1
FBOUT_NC
FBOUT_NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
GND 16
Si53115
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VDD_IO
GND
DIF_9
DIF_9
DIF_8
DIF_8
GND
VDD
DIF_7
DIF_7
DIF_6
DIF_6
VDD_IO
GND
DIF_5
DIF_5
Patents pending
Rev. 1.1 12/15
Copyright © 2015 by Silicon Laboratories
DIF_0 17
DIF_0 18
VDD_IO 19
GND 20
DIF_1 21
DIF_1 22
DIF_2 23
DIF_2 24
GND 25
VDD 26
DIF_3 27
DIF_3 28
DIF_4 29
DIF_4 30
VDD_IO 31
GND 32
Si53115
S i 5 3 11 5
Functional Block Diagram
FB_OUT
SSC Compatible
PLL
CLK_IN
CLK_IN
DIF_[14:0]
100M_133
HBW_BYPASS_LBW
SA_0
SA_1
PWRGD / PWRDN
SDA
SCL
Control
Logic
2
Rev. 1.1
Si53115
T
ABLE
Section
OF
C
ONTENTS
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1. CLK_IN, CLK_IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2. 100M_133M—Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3. SA_0, SA_1—Address Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4. CKPWRGD/PWRDN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5. HBW_BYPASS_LBW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.6. Miscellaneous Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3. Test and Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1. Input Edge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2. Termination of Differential Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.1. Byte Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2. Block Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.3. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5. Pin Descriptions: 64-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6. Power Filtering Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.1. Ferrite Bead Power Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Rev. 1.1
3
S i 5 3 11 5
1. Electrical Specifications
Table 1. DC Operating Characteristics
V
DD_A
= 3.3 V±5%, V
DD
= 3.3 V±5%
Parameter
3.3 V Core Supply Voltage
3.3 V I/O Supply Voltage
1
3.3 V Input High Voltage
3.3 V Input Low Voltage
Input Leakage Current
2
3.3 V Input High Voltage
3
3.3 V Input Low Voltage
3
3.3 V Input Low Voltage
3.3 V Input Med Voltage
3.3 V Input High Voltage
3.3 V Output High Voltage
4
3.3 V Output Low Voltage
4
Input Capacitance
5
Output Capacitance
5
Pin Inductance
Ambient Temperature
Symbol
VDD/VDD_A
VDD_IO
V
IH
V
IL
I
IL
V
IH_FS
V
IL_FS
V
IL_Tri
V
IM_Tri
V
IH_Tri
V
OH
V
OL
C
IN
C
OUT
L
PIN
T
A
Test Condition
3.3 V ±5%
1.05 V to 3.3 V ±5%
VDD
0 < VIN < V
DD
V
DD
Min
3.135
0.9975
2.0
VSS–0.3
–5
0.7
VSS–0.3
0
1.2
2.2
Max
3.465
3.465
V
DD
+0.3
0.8
+5
V
DD
+0.3
0.35
0.8
1.8
V
DD
—
0.4
4.5
4.5
7
70
Unit
V
V
V
V
µA
V
V
V
V
V
V
V
pF
pF
nH
°C
I
OH
= –1 mA
I
OL
= 1 mA
2.4
—
2.5
2.5
—
No Airflow
0
Notes:
1.
VDD_IO applies to the low-power NMOS push-pull HCSL compatible outputs.
2.
Input Leakage Current does not include inputs with pull-up or pull-down resistors. Inputs with resistors should state
current requirements.
3.
Internal voltage reference is to be used to guarantee V
IH
_FS and V
IL
_FS thresholds levels over full operating range.
4.
Signal edge is required to be monotonic when transitioning through this region.
5.
Ccomp capacitance based on pad metalization and silicon device capacitance. Not including pin capacitance.
4
Rev. 1.1
Si53115
Table 2. SMBus Characteristics
Parameter
SMBus Input Low Voltage
1
SMBus Input High Voltage
1
SMBus Output Low Voltage
1
Nominal Bus Voltage
1
SMBus Sink Current
1
SCLK/SDAT Rise Time
1
SCLK/SDAT Fall Time
1
SMBus Operating Frequency
1, 2
Symbol
V
ILSMB
V
IHSMB
V
OLSMB
V
DDSMB
I
PULLUP
t
RSMB
t
FSMB
f
MINSMB
@ I
PULLUP
@ V
OL
3 V to 5 V +/-10%
(Max V
IL
– 0.15) to (Min V
IH
+ 0.15)
(Min V
IH
+ 0.15) to (Max V
IL
– 0.15)
Minimum Operating Frequency
100
2.7
4
1000
300
2.1
Test Condition
Min
Max
0.8
V
DDSMB
0.4
5.5
Unit
V
V
V
V
mA
ns
ns
kHz
Notes:
1.
Guaranteed by design and characterization.
2.
The differential input clock must be running for the SMBus to be active.
Table 3. Current Consumption
T
A
= 0–70 °C; supply voltage V
DD
= 3.3 V ±5%
Parameter
Operating Current
Symbol
IDD
VDD
IDD
VDDA
IDD
VDDIO
Test Condition
133 MHz, VDD Rail
133 MHz, VDDA + VDDR, PLL Mode
133 MHz, CL = Full Load, VDD IO Rail
Power Down, VDD Rail
Power Down, VDDA Rail
Power Down, VDD_IO Rail
Min
—
—
—
—
—
—
Typ
25
20
100
0.5
4
0.4
Max
30
25
110
1
7
0.7
Unit
mA
mA
mA
mA
mA
mA
Power Down Current
IDD
VDDPD
IDD
VDDAPD
IDD
VDDIOPD
Rev. 1.1
5
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