Si51218
T
HREE
O
UTPUTS
F
ACTORY
P
R O GRA MM A B LE
C
LOCK
G
ENERATOR
Features
Generates up to 3 LVCMOS
Separate voltage supply pins
clock outputs from 32.768 kHz to
V
DD
= 2.5 to 3.3 V
200 MHz
V
DDO
= 1.8 to 3.3 V (V
DDO
≤
V
DD
)
Accepts crystal or reference
Low cycle-cycle jitter
clock input
Programmable output rise and
to 166 MHz reference clock input
3
fall times
8 to 48 MHz crystal input
Ultra small 8-pin TDFN package
Programmable FSEL, PD and
(1.4 mm x 1.6 mm)
OE input functions
Operation temperature: 0–70
C
Low power dissipation
Applications
Crystal / XO replacement
Digital Media players
Ordering Information:
See page 10.
Portable Devices
DTV/IPTV
Pin Assignments
VDDO
CLKOUT3
CLKOUT2/REFOUT2
FSEL/OE/PD#
VSS
Description
The factory programmable Si51218 is a low power, small footprint and
frequency flexible programmable clock generator targeting low power, low
cost and high volume consumer and embedded applications. The device
operates from a single crystal or an external clock source and generates
up to 3 clock outputs from 32.768 kHz to 200 MHz. They are factory
programmed to provide customized output frequencies, control inputs and
ac parameter tuning like output drive strength that are optimized for
customer board condition and application requirements. A separate
VDDO supply pin supports clock outputs at a different voltage level.
VDD
XOUT
XIN/CLKIN
CLKOUT1/REFOUT1
FSEL/OE
1
2
8
7
Si51218
3
4
6
5
Patents pending
Functional Block Diagram
XIN/CLKIN
3
PLL with
Modulation Control
Buffers,
Dividers
and
Switch
Matrix
To Pin 6/7 Clock Drivers
4
CLKOUT1/REFOUT1 (VDD)
OE/FSEL
XOUT
2
6
CLKOUT2/REFOUT2(VDDO)
OE/FSEL/PD#
VDDO
8
VDD
1
Program able
m
Configuration Register
7
CLKOUT3(VDDO)
V-Reg
To Core
To Pin 4 Clock Driver and
Oscillator
VSS
5
Rev. 1.0 3/14
Copyright © 2014 by Silicon Laboratories
Si51218
Si51218
T
ABLE
Section
OF
C
ONTENTS
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3.1. Input Frequency Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3.2. Output Frequency Range and Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3.3. Frequency Select (FSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3.4. Power Down (PD) or Output Enable (OE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4. Pin Descriptions—8-Pin TDFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
5. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6. Package Outline: 8-pin TDFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7. PCB Land Pattern: 8-pin TDFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Rev. 1.0
3
Si51218
1. Electrical Specifications
Table 1. DC Electrical Specifications
(V
DD
=3.3 V ± 10% or V
DD
=2.5 V ± 5%, T
A
=0 to 70
o
C)
Parameter
Operating Voltage
Symbol
V
DD
V
DDO
Test Condition
V
DD
=3.3 V ±10%
V
DD
=2.5 V ±5%
V
DDO
≤
V
DD
I
OH
= –4 mA,
V
DDX
=V
DD
or V
DDO
I
OL
= 4mA,
CMOS level
CMOS level
F
IN
=20 MHz, CLK-
OUT1=32.768KHz,
REFOUT2=20 MHz CLK-
OUT3=26MHz, C
L
=0,
V
DD
=V
DDO
=3.3 V
Pin 6
Input Pin Capacitance
Clock outputs < 166 MHz
Clock outputs > 166 MHz
Min
2.97
2.375
1.71
V
DDX
-0.5
—
0.7 V
DD
—
—
Typ
3.3
2.5
—
—
—
—
—
6
Max
3.63
2.625
3.6
—
0.3
—
0.3 V
DD
—
Unit
V
V
V
V
V
V
V
mA
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
Operating Supply Current
V
OH
V
OL
V
IH
V
IL
I
DD
Nominal Output Impedance
Internal Pull-up/Pull-down
Resistor
Input Pin Capacitance
Load Capacitance
Z
O
R
PUP
/R
PD
C
IN
C
L
—
—
—
—
—
30
150k
3
—
—
—
—
5
15
10
pF
pF
pF
4
Rev. 1.0
Si51218
Table 2. AC Electrical Specifications
(V
DD
=3.3 V ± 10% or V
DD
=2.5 V ± 5%, T
A
=0 to 70
o
C)
Parameter
Input Frequency Range
Input Frequency Range
Output Frequency Range
Frequency Accuracy
Output Duty Cycle
Input Duty Cycle
Output Rise Time
Output Fall Time
Period Jitter
Period Jitter
Cycle-to-Cycle Jitter
Power-up Time
Output Enable Time
Output Disable Time
Symbol
F
IN1
F
IN2
F
OUT
F
ACC
DC
OUT
DC
IN
t
r
t
f
PJ
1
PJ
2
CCJ
t
PU
t
OE
t
OD
Test Condition
Crystal input
Reference clock Input
Configuration dependent
Measured at V
DD/2
CLKIN, CLKOUT through PLL
CLKOUT1/2/3 in MHz range
C
L
=15 pF, 20 to 80%
CLKOUT1/2/3 in MHz range
C
L
=15 pF, 20 to 80%
CLKOUT1/2/3 in MHz range,
V
DD
=V
DDO
=3.3 V, CL=15 pF
CLKOUT1/3 at 32.768KHz,
V
DD
=V
DDO
=3.3 V, CL=15 pF
CLKOUT1/2/3, in MHz range
V
DD
=V
DDO
=3.3 V, CL=15 pF
Time from 0.9 V
DD
to valid fre-
quencies at all clock outputs
Time from OE raising edge to
active at outputs (asynchronous)
Time from OE falling edge to
active at outputs (asynchronous)
Min
8
3
0.032768
—
45
30
—
—
—
—
—
—
—
—
Typ
—
—
—
0
50
50
1
1
150
*
1500
*
100
*
1.2
15
15
Max
48
166
200
—
55
70
3.0
3.0
—
—
—
5.0
—
—
Unit
MHz
MHz
MHz
ppm
%
%
ns
ns
ps
ps
ps
ms
ns
ns
*Note:
Jitter performance depends on configuration and programming parameters.
Rev. 1.0
5
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