AN610
Si48
XX
ATD D P
ROGRAMMING
G
U ID E
1. Introduction
1.1. Scope
This document provides an overview of the programming requirements for the Si4822/26/27/40/44 analog tune
digital display (ATDD) AM/FM/SW receiver. The hardware control interface and software commands are detailed
along with several examples of the required steps to configure the device for various modes of operation.
2. Overview
The Si4822/26/27/40/44 family of products is programmed using commands and responses. To perform an action,
the system controller writes a command byte and associated arguments, causing the device to execute the given
command. The device will, in turn, provide a response depending on the type of command that was sent. Section
“6. Commands and Responses” and Section “7. Commands and Properties” describe the procedures for using
commands and responses and provide complete lists of commands, properties, and responses.
The device has a slave control interface that allows the system controller to send commands to and receive
responses from the device using 2-wire mode (I
2
C and SMBUS compatible) serial protocol (or bus modes).
The following sections provide guidelines for programming the ATDD device:
"4. ATDD Device Overview" on page 4 gives an overview of the ATDD device.
Section "5. ATDD Device Power On/Off and Band Switch Overview" on page 7 gives an overview of the
Power on / off and the band switching sequencing for the ATDD device.
Section "8. Control Interface" on page 55 describes the control interface in details.
Section "9. Powerup" on page 58 describes the options for the sequencing of VDD and VIO power
supplies, provision of the reference clock, RCLK, and sending of the ATDD_POWER_UP command.
Section "10. Powerdown" on page 59 describes sending of the POWER_DOWN command and removing
VDD and VIO power supplies as necessary.
Section "11. Programming Example" on page 60 provides the flowcharts and step-by-step procedures for
programming the device.
Note:
The ATDD family has its own power up and getting status commands which are different from previous Si47xx DTDD
family. To differentiate, we use “ATDD_POWER_UP” and ATDD_GET_STATUS to denote the ATDD specific commands
instead of the general Si47xx “POWER_UP” and “STATUS” commands.
Section
Rev. 0.3 3/13
Copyright © 2013 by Silicon Laboratories
AN610
AN610
Table 1. Product Family Function
EN55020 Compliance
Part Number
General Description
Wide SW Bands
Wide FM Bands
SW Receiver
AM Receiver
FM Receiver
Stereo FM
China TV Channel Audio
Package
Size
Si4822
Si4826
Si4827
Si4840
Si4844A*
Si4844B*
AM/FM Receiver
AM/SW/FM Receiver
AM/SW/FM Receiver
AM/FM Receiver
AM/SW/FM Receiver
AM/SW/FM Receiver
SSOP-24
SSOP-24
SOIC-16
SSOP-24
SSOP-24
SSOP-24
*Note:
New features have been added to Si4844-B20 that are not available in the older Si4844-A10 part.
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3. Terminology
Digital Tune Digital Display
ATDD— Analog Tune Digital Display
ATAD— Analog Tune Analog Display
SDIO—
SCLK—
DTDD—
2-wire bus mode Serial data in/data out pin (Compatible to I
2
C SDA pin)
2-wire bus mode Serial clock pin (Compatible I
2
C SCL pin)
RST or RSTb—Reset pin, active low
IRQ— Interrupt request pin, active high
RCLK—External reference clock
CTS—Clear to send
NVM—Non-volatile internal device memory
Device—Refers to the AM/FM/SW Receiver
System Controller—Refers to the system microcontroller
CMD—Command byte
COMMANDn—Command register (16-bit) in 3-Wire mode (n = 1 to 4)
ARGn—Argument byte (n = 1 to 7)
STATUS—Status byte
RESPn—Response byte (n = 1 to 15)
RESPONSEn—Response register (16-bit) in 3-Wire mode (n = 1 to 8)
Rev. 0.3
3
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4. ATDD Device Overview
The Si4822/26/27/40/44 devices are the tuner ICs for the analog tune digital display (ATDD) market. The Si4822/
26/27 are the consumer grade FM mono parts and are not EN55020 compliance.
In general, any commands and properties associated with setting FM stereo/mono modes and FM blending sent to
the ATDD mono parts will simply be ignored and will not have effects. Also, the commands for getting the FM
stereo status of a tuned channel is always "mono" for these parts. This effect will not be specified again in the rest
of the document.
The ATDD device has two operating modes of band detection configuration options: either the ATDD device
detects the band or the system controller detects and controls the band by its own mechanism. The diagrams
below illustrate how the ATDD device works in each mode.
RSTb
PVR Tune wheel
Host MCU
(Master)
IRQ
SCLK
SDIO
ATDD Tuner
(Slave)
Band switch
Resistor ladder
Figure 1. ATDD Device is Responsible for Band Detection
Band select
FM
AM
Host MCU
(Master)
RSTb
IRQ
SCLK
SDIO
ATDD Tuner
(Slave)
PVR Tune wheel
VDD1
Figure 2. System Controller is Responsible for Band Detection
Each of these two operating modes requires different hardware configuration. For the ATDD device, the BAND pin
of the device must be connected to the band switch resistor or to the power supply pin instead, i.e. VDD1 for
Si4822/26/40/44 and VDD for Si4827. At power up, the system controller is required to read the band configuration
state bits from the ATDD device and determine which configuration option is responsible for the band detection.
The ATDD device is a slave device which requires a host system controller to control it, similar to the Si47xx DTDD
family. The communication between the host and the salve devices is via the 2-wire bus mode. Unlike the Si47xx
DTDD devices, the ATDD device has its own PVR based tune wheel and resistor ladder based band switch. The
ATDD device reads the band switch resistor ladder to determine the frequency band and then reads the PVR tune
wheel position for channel tuning. When the ATDD device senses a change in either the PVR tune wheel position
or the band switch position, it will send out an interrupt request to the host system controller. The system controller
then issues a get status command to read the updated tuned frequency and band status for display on its LCD or
LED.
The communication interface between the system controller and the ATDD device is the 2-wire bus mode interface.
The hardware interface pins of the ATDD device are described in Table 2:
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Rev. 0.3
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Table 2. ATDD Device Hardware Interface
Pin Name
RSTb
IRQ
SDIO
SCLK
Function
Device reset input (active low)
Host interrupt request output (active high)
2-wire bus mode serial data input/output
2-wire bus mode serial clock input (Note: ATDD device is
slave)
The ATDD device is a slave device and its seven-bit device address is (0010001b). To achieve acceptable or
higher tune frequency update performance, the system controller 2-wire bus mode clock speed of 10 kHz* or
higher is recommended. The ATDD device requires a 32.768 kHz clock supply of 100 ppm for proper radio
operation. The system controller can configure the ATDD device by applying an external reference clock to the
device (various frequencies can be selected) or by using a 32.768 kHz crystal instead.
The ATDD device has flexibility in selecting bands and configuring band properties, such as band top, band
bottom, and channel spacing. In addition, the Si4822/26/40/44 SSOP24 packaged parts have a pull up resistor
option (at pin 1 LNA_EN) to force the ATDD device to use its default band properties rather than the values
programmed by the system controller. For example, when the ATDD device pin 1 is pulled up, it will ignore the
band properties programmed by the system controller programmed (band top, band bottom, channel space, FM
de-emphasis, and FM blend RSSI mono/stereo thresholds). The system controller is able to read this information
from the band configuration state bits from the ATDD device. The Si4827 SOIC16 package ATDD part doesn't have
the pin pull-up option. However, the host controller can send an extra argument byte in the ATDD_POWER_UP
command to specify this band properties priority.
*Note:
The ATDD device requires a slower I
2
C clock for proper powerup immediately after a hardware reset; i.e., no higher
than 10 kHz is recommended. After the powerup command sequence is succeeded, the host controller can switch to a
higher speed.
To power up the ATDD device for higher I2C clock speed, the host controller needs to obey more strict timing
requirements as below:
1. After reset, the host controller needs to wait till the first IRQ pulse is finished before sending a command;
i.e. send a command after the IRQ falling edge or wait 2.5 ms after the IRQ rising edge.
2. The pulse width of the I
2
C clock signal (i.e., high to low level ratio) must be equal or greater than 50%.
3. After sending either the ATDD_GET_STATUS command 0xE0 or the ATDD_POWER_UP command 0xE1,
the host controller needs to wait for 2 ms before polling response byte CTS bit or reading the response
directly.
Following the above timing requirements, the ATDD device is tested by powering up successfully for I
2
C clock
speed up to 50 kHz. Clock speed higher than 50 kHz is possible but is not guaranteed. After reset and the first
successful powerup, the host controller is free to switch to a higher I
2
C speed and shorter CTS polling interval
(down to 50 µs is recommended).
Customers using 10 kHz I
2
C clock speed or below for powerup are not required to change their existing host
controller firmware with respect to the new timing requirements.
Rev. 0.3
5
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