DEMO MANUAL DC1954A
LTC6954
Low Phase Noise, Triple Output Clock
Distribution Divider/Driver
Description
Demonstration Circuit 1954A features the
LTC
®
6954,
a
Low Phase Noise, Triple Output Clock Distribution Divider/
Driver.
There are four options of the DC1954A, one for each ver-
sion of the LTC6954. Table 1 summarizes the available
DC1954A options.
The DC1954A LVPECL outputs are AC-coupled 50Ω
transmission lines making them suitable for driving 50Ω
impedance instruments. The LVDS/CMOS outputs of the
DC1954A are terminated with a 100Ω differential resistor
and are DC-coupled. All differential input and outputs have
3.3V DC Supply,
banana jack &
turret
0.5" spaced SMA connectors. The LTC6954’s EZSync™
function is made available via a turret and an SMA con-
nector.
A DC590 USB serial controller board is used for SPI
communication with the LTC6954, controlled by the
supplied LTC6954_GUI software.
Design files for this circuit board are available at
http://www.linear.com/demo/DC1954A
L,
LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and EZSync
is a trademark of Linear Technology Corporation. All other trademarks are the property of their
respective owners.
GND, banana
jack & turret
Ribbon
cable
connection
to DC590
OUT0 Outputs, SMA
LTC6954‐1/‐2/‐3
LVPECL, AC coupled
LTC6954‐4
LVDS/CMOS, DC coupled
IN Inputs, SMA
AC coupled
OUT1 Outputs, SMA
LTC6954‐1/‐2
LVPECL, AC coupled
LTC6954‐3/‐4
LVDS/CMOS, DC coupled
EZSync
TM
SYNC Input,
SMA & turret
Temperature
monitoring diode, turret
OUTxSEL Inputs, Headers
For LVPECL OUTPUTS:
H=IBIAS ON; L=IBIAS OFF
For LVDS/CMOS OUTPUTS:
H=LVDS; L=CMOS
OUT2 Outputs, SMA
LTC6954‐1
LVPECL, AC coupled
LTC6954‐2/‐3/‐4
LVDS/CMOS, DC coupled
Figure 1. DC1954A Connections
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DEMO MANUAL DC1954A
Quick start proceDure
The DC1954A is easy to set up to evaluate the performance
of the LTC6954. Follow the procedure below.
The DC590 and LTC6954_GUI application are required to
control the DC1954A through a personal computer (PC).
DC590 Configuration
Place the DC590 jumpers in the following positions (refer
to Figure 2):
JP4:
EE
JP5:
ISO
JP5:
SW
Must be in the EN position.
ON must be selected.
ON must be selected.
Connect the DC590 to one of your computer’s USB ports
with the included USB cable.
LTC6954_GUI Installation
The LTC6954_GUI software is used to communicate with
the LTC6954. It uses the DC590 to translate between USB
and SPI-compatible serial communications formats. The
following are the LTC6954_GUI system requirements:
•
Windows Operating System: Windows XP, Windows
2003 Server, Windows Vista, Windows 7
•
Microsoft .NET 3.5 SP1 or later
•
Windows Installer 3.1 or later
•
Linear Technology’s DC590 hardware
JP6:
VCCIO 3.3V or 5V must be selected. This sets the
SPI port to 3.3V or 5V operation, 3.3V
operation is recommended.
Figure 2. DC590 Jumper and Connector Locations
2
dc1954af
DEMO MANUAL DC1954A
Quick start proceDure
Download the LTC6954_GUI setup file at:
www.linear.com/LTC6954_GUI.
Run the LTC6954_GUI setup file and follow the instructions
given on the screen. The setup file will verify and/or install
Microsoft .NET and install the LTC6954_GUI.
DC1954A Configuration
1. Connect the GND and V+ 3.15V-3.45V, turrets to a
power supply and apply power (see Figure 1 and the
Typical DC1954A Requirements and Characteristics
table).
2. Connect the DC590 to the DC1954A with the provided
ribbon cable.
3. Run the LTC6954_GUI application.
4. From the LTC6954_GUI, click
File -> Load Settings
and point to the LTC6954.6954set file.
5. From the LTC6954_GUI, select the Read All button.
This will update the GUI to display the correct part
number and associated output types.
6. Connect a low phase-noise (or jitter) single-ended or
differential signal to IN+ (J8) and/or IN- (J9). Refer to
the LTC6954 data sheet for acceptable input frequen-
cies and amplitudes.
7. From the LTC6954_GUI, update Fin to the frequency
of the input signal in step 6. This will update the
LTC6954_GUI with the correct output frequencies.
8. Refer to the Typical DC1954A Requirements and
Characteristics table for desired OUTxSEL level. Set
JP1, JP2 and JP3 accordingly.
9. Connect desired output (OUT0, OUT1, OUT2) to a test
instrument or other demo board to evaluate perfor-
mance.
[The LVDS/CMOS outputs are DC-coupled,
please make sure the levels do not exceed the test
equipment input levels].
10. To synchronize outputs provide a 1ms or greater
high pulse to the SYNC SMA to take advantage of the
EZSync function.
Be sure to power down or terminate any unused RF output
with 50Ω, or poor spurious performance may result.
Figure 3. LTC6954_GUI Screenshot
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DEMO MANUAL DC1954A
Quick start proceDure
Troubleshooting
If the board is not functioning as expected, follow the
instructions below:
1. Verify that you are able to communicate with the
DC1954A. The bottom status line in LTC6954_GUI
should read LTC6954 and Comm Enabled.
2. Verify that V+ 3.15V-3.45V turret has the correct
voltage. (see the Typical DC1954A Requirements and
Characteristics table).
3. Ensure JP1, JP2, and JP3 are set to desired position.
4. If the output type is LVPECL and the output is AC-coupled,
OUTxSEL must be high for proper signal swing.
5. If the output type is LVDS, the outputs must be AC-coupled
into single-ended, 50Ω input test equipment. Additionally,
the unconnected output must be AC-coupled into a 50Ω
load to ground to provide a balanced output load. If the
LVCSx bit is low, the signal amplitude at the instrument
will be approximately half of the data sheet value due to
the existing 100Ω termination on the demo board.
6. If the output is CMOS, a 200Ω series resistor must be
included to limit the output current when connecting
to the 50Ω input on test equipment. The signal swing
at the instrument is then approximately 20 percent of
the data sheet value.
Contact the factory for further troubleshooting.
Dc1954a reconfiguration
The DC1954A allows for a variety of input and output
configurations. The following covers the hardware recon-
figuration of the DC1954A.
LVPECL Output Options
The DC1954A LVPECL outputs are AC-coupled and require
internal biasing (OUTxSEL=H) with the default termination
network. The DC1954A provides pull-down, series and a
differential termination resistor options to accommodate
the other LVPECL termination networks described in the
data sheet.
LVDS/CMOS Output Options
The LVDS/CMOS outputs are DC-coupled and have an on
board differential 100Ω resistor termination by default. The
DC1954A provides pull-down, series and a differential ter-
mination resistor options to accommodate the other LVDS/
CMOS termination networks described in the data sheet.
Input Options
The inputs have a 50Ω termination resistor to GND and are
AC-coupled by default. The DC1954A provides pull-down,
pull-up and a differential termination resistor options to
accommodate the other input termination networks de-
scribed in the data sheet.
Clock Follower Input Network
When using the DC1954A as a clock follower, EZSync
requires the LTC6954 inputs to be taken to a low state
while the SYNC pin is high. To meet this requirement, the
DC1954A must be modified to support DC-coupling. Refer
to the EZSync Function section and to the data sheet for
more details on using the LTC6954 as a clock follower.
EZSync Function
Apply a 1ms or greater high pulse to the SYNC SMA con-
nector to take advantage of the EZSync function. Refer
to the LTC6954 data sheet for SYNC timing and level
requirements.
assembly options
Table 1. DC1954A Assembly Options
ASSEMBLY VERSION
DC1954A-A
DC1954A-B
DC1954A-C
DC1954A-D
U1 PART NUMBER
LTC6954IUFF-1
LTC6954IUFF-2
LTC6954IUFF-3
LTC6954IUFF-4
OUT0+/–
LVPECL
LVPECL
LVPECL
LVDS/CMOS
OUT1+/–
LVPECL
LVPECL
LVDS/CMOS
LVDS/CMOS
OUT2+/–
LVPECL
LVDS/CMOS
LVDS/CMOS
LVDS/CMOS
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DEMO MANUAL DC1954A
typical Dc1954a reQuirements anD characteristics
PARAMETER
INPUT OR OUTPUT PHYSICAL LOCATION
J11 and J10 Banana Jacks, or 3.15V-3.45V and
GND Turrets
J1 and J2 SMA Connectors*
J3 and J4 SMA Connectors*
J5 and J6 SMA Connectors*
DETAILS
Low-Noise and Spur-Free 3.3V, ≥400mA Capable Power
Supply; Typically DC1954 Consumes ~300mA; Powers
LTC6954, U2, U3, and U4
Refer to Figure 1 or Table 1 for Output Type
If LVPECL:
AC-Coupled
If LVDS/CMOS:
DC-Coupled
Refer to LTC6954 Data Sheet for Output Levels for LVPECL, or
LVDS/CMOS Option
OUT0SEL
OUT1SEL
OUT2SEL
Input
Input
Input
JP1 3-Pin Headers
JP2 3-Pin Headers
JP3 3-Pin Headers
If LVPECL:
OUTxSEL=H: IBIAS=ON, for Default LVPECL BOM
OUTxSEL=L: IBIAS=OFF, Must Install External Pull-Down
Resistor, Refer to schematic
If LVDS/CMOS:
OUTxSEL=H: LVDS, Default LVDS/CMOS BOM
OUTxSEL=L: CMOS, Remove 100Ω Differential Termination,
Refer to Schematic
TEMP
TEMP GND
SYNC
IN+, IN–
Input/Output
Input
Input
Input
Turret
Turret
J7 SMA Connector and Turret
J8 and J9 SMA Connectors
Temperature Monitoring Diode; Force Current Measure
Voltage, Refer to Data Sheet
EZSync, 0V to 3.3V Control Signal, Refer to the Data Sheet
Input Signal Pins
3.3V Power Supply Input
OUT0+, OUT0–
OUT1+, OUT1–
OUT2+, OUT2–
Two Outputs
Two Outputs
Two Outputs
*Any unused RF output
must
be powered down or terminated with 50Ω, or poor spurious performance may result.
pcb layout
Top Layer
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