AN851
Si468
X
S
CHEMATICS
1. Introduction
This document provides the following:
General
AND
L
AYOUT
G
UIDE
Si468x design guidelines, which include schematics, layout, and BOM
Si468x AM/AMHD-FM/FMHD-DAB/DAB+ antenna/matching network design guidelines
2. Si468x QFN Schematic and Layout
2.1. Schematic design and component selection
This section shows the minimal schematic and layout options reserved for optimal performance of the Si468x in the
QFN package. Population options are provided to mitigate on-chip VCO radiated emissions, to use analog audio
output, and to operate the Si468x with crystal.
2.1.1. Schematic Design
4
3
2
1
VCORE
VIO
EPAD 49
NVMOSI 48
47
NVMISO
46
DCLK2
45
DFS2
44
DOUTA2
43
DOUTB2
42
TSCLK
41
TSSYNC
40
TSVAL
39
TSDATA
38
CLKOUT
37
VCORE
VMEM_C
B
J1 is used for FM/DAB Testing
FM/DAB Matching Option
J1
C1
B
C7
8.2pF
C10
C6
C9
8.2pF 2.2nF
DBYP 36
35
VMEM
34
VIO
33
DOUT
32
MISO
31
MOSI
30
SCLK
29
SSB
28
DFS
27
DCLK
26
DIN
25
DIFS
2.2nF
C23
1uF
C22
1uF
C8
8.2pF
C11
2.2nF
C24
1uF
L4
18nH
L1
120nH
L2
C15
VHFI
SMA_EDGE
33pF
22nH
2.7pF
D1
1
CM1210
CH1
Optional
VHFSW
1
2
3
4
5
AMLOOPN
6
AMLOOPP
7
8
9
10
11
12
NVSSB
NVSCLK
INTB
RSTB
SMODE
LOOPN
LOOPP
WHIP
RFREF
VHFI
VHFSW
VA
U1
SI46xx
2
VP
VN
3
VA
C4
C3
C2
1uF
2.2nF 8.2pF
J2
J8
1
T2
6
5
R60 0
R61
0
19.2MHZ
X1
XTAL_OUT
SMA_EDGE
R57
49.9
3
4
TTBW2010L
1:1
13
ABYP
14
NC
15
XTALI
16
XTALO
17
DACREF
18
LOUT
19
ROUT
20
ICIP
21
ICIN
22 MSCL
23 MSDA
24
DICLK
Optional
T1
6
J11
1
FB5
1uF
C20
R56
NP
AMLOOPN
1000_ohm_Ferrite
DIAG_A
AMLOOPP
C5
C13
ROUT
4
3
R62
NP
SL755TF01
A
Optional
1uF
8.2pF
A
1uF
FB6
C21
Population Options for AM Front End
Conducted Test
---------------------
Default
Radiated Test using Loop Antenna
---------------------
Populate R56, R62
Remove R60, R61
Radiated Test using Ferrite Antenna
---------------------
Remove R60, R61, R56, R62
1000_ohm_Ferrite
LOUT
Silicon Laboratories, Inc.
400 West Cesar Chavez
Austin, Texas 78701 USA
+1 512 416 8500
TITLE
C12
8.2pF
Optional
SIZE
Si46xx QFN Daughter Card
DWG NO
Confidential
All Material and information contained herein
is confidential and covered under non-disclosure agreement (NDA)
DRAWN BY
SCALE
B
1.1
SHEET
Rev 4.0
1
of
2
13-05-2014_14:12
4
3
2
1
Figure 1. Si468x QFN Schematic Design
Rev. 0.2 11/14
Copyright © 2014 by Silicon Laboratories
AN851
AN851
3. EMI Mitigation
Due to a high frequency (2880–3840 MHz) on-chip VCO, there is some conductive and magnetic coupling from the
VCO to the adjacent traces. The VCO fundamental spur level can be reduced by adding external filtering and using
the proper layout.
3.1. External filtering
Add
filter network comprising of L4 and C15 on the RF input trace (VHFI) for filtering the VCO spur
(2880–3840 MHz). The capacitance C15 provides a low impedance path to ground, and inductor L4
provides high impedance to the VCO spur. The inductor L4 also helps in protecting the chip from an
external ESD event by providing high impedance path to the ESD event. The two component network
attenuates the VCO spur from reaching external antenna port and radiating out. The values of these
components are selected to achieve the balance between the sensitivity and the emission levels.
Add low pass network C13 & FB5 and C12 & FB6 on the audio lines Right and Left respectively for
attenuating the VCO coupling
Add high Self Resonant Frequency (>3 GHz) capacitors C2, C6, C7 and C8 on the supply lines to decouple
the VCO leakage currents.
3.2. Front-End Matching
The components (C1, L1, L2, and L4) are used for maximizing the voltage gain on the VHFI pin.
For the FM and DAB band, the matching components C1, L1, L2, and L4 will require optimization to maximize the
voltage gain on the VHFI pin. The inductor L2 can be engaged or disengaged using a VHFSW switch. Refer to
property “0x1712” of AN649 for information on how to handle the VHFSW switch. The voltage gain is maximized by
forming a high Q parallel LC resonant tank circuit. The inductor of the tank circuit is the parallel combination of L1
and L2. And the tank capacitance includes the antenna capacitance, capacitance of the external front end network,
PCB parasitic, internal chip parasitic and internal variable capacitance provided by on-chip varactor tuning.
With a given antenna source impedance and the parasitics (pcb and chip internal), the resonant peak of the LC
tank circuit across the FM and DAB band can be maximized by finding the right combination of C1, L1, L2, and L4,
and the internal varactor capacitance. Refer to Appendix A for additional details on using internal varactor tuning.
Note that the procedure outlined in Appendix A for internal varactor tuning is considering the signal generator
source impedance (50
)
but the same procedure can be used with different antenna source impedance. Refer to
Appendix B on how to select component values for optimizing the front end.
2
Rev. 0.2
AN851
Table 1. Application Schematic BOM
Ref Designator
C1
L4
C15
L1
L2
C2,C6,C7,C8,C12
and C13
FB5 and FB6
C3,C9,C10 and C11
C1, C20, C21, C22,
C23, and C24
X1
T2
Description
CAP,SM,0402
IND,SM,0402
CAP,SM,0402
IND,SM,0402
IND,SM,0402
CAP,SM,0402
Ferrite, 0402
CAP,SM,0402
CAP,SM,0402
Crystal
Transformer for con-
ducted measurement
using signal generator
Transformer for radiated
measurements with loop
antenna
RES, SM, 0402
Value
33 pF
18 nH
2.7 pF
120 nH
22 nH
8.2 pF
1000 ohm
2.2 nF
1 µF
19.2
1:1
Manufacture Part #
C0402C0G500-330JNP
LQG15HS18NJ02D
GJM1555C1H2R7BB01D
LQW15ANR12J00D
LQW15AN22NH00D
GRM1555C1H8R2DA01D
BLM15HG102SN1D
C0402X7R500-222KNP
C1005X5R1C105K050BC
Abracon, ABM8-19.200MHz-
10-1-U_T, 19.2 MHz
TTBW2010
T1
1:6
SL755TF01
R56 and R62
0
CR0402-16W-000T
Rev. 0.2
3
AN851
3.2.1. Component Selection and Replacement
The front end network components shall be placed as close as possible to the chip and as far away from noise
sources such as clocks and digital circuits. L1 shall be routed to ground plane with a short trace and a via
connection.
The recommendations regarding C1, C2, C3, C5, C6, C7, C8, C9 and C10 are made to reduce the size of the
current loop created by the bypass cap and routing, minimize impedance and return all currents to the ground.
C3 and C4 (2.2 nF and 1 uF) are
required
bypass capacitors for VA supply pin 12. Place C2, C3 and C4 as close
as possible to VA. C3 and C4 are chosen to mitigate noise in medium to VHF frequency range. Place a via
connecting C2, C3, C4 and VA pins to the power rail such that the caps are closer to the Si468x VA pin than the via.
Route C2, C3 and C4 only to the ABYP pin directly with a short (6-mil width) low inductance trace.
C9 and C22 (2.2 nF and 1 uF) are
required
bypass capacitors for VIO supply pin 34. C9 and C22 are chosen to
mitigate noise in medium to VHF frequency range. Place C6, C9, and C22 as close as possible to VIO pin 34 and
DBYP pin 36. Place a via connecting C6, C9, and C22 and VIO supply to the power rail such that the caps are
closer to the Si468x VIO pin than the via. Route C6, C9, and C22 only to DBYP pin directly with a short (6-mil
width) low inductance trace.
C10 and C23 (2.2nF and 1 uF) are
required
bypass capacitors for VMEM supply pin 35. C10 and C23 are chosen
to mitigate noise in medium to VHF frequency range. Place C7, C10, and C23 as close as possible to VMEM pin
35 and DBYP pin 36. Place a via connecting C7, C10, and C23 and VMEM supply pin to the power rail such that
the caps are closer to the Si468x VMEM pin than the via. Route C7, C10, and C23 only to DBYP pin directly with a
short (6-mil width) low inductance trace.
C11 and C24 (2.2nF and 1 uF) are
required
bypass capacitors for VCORE supply pin 37. C11 and C24 are chosen
to mitigate noise in medium to VHF frequency range. Place C8, C11 and C24 as close as possible to VCORE pin
37 and DBYP pin 36. Place a via connecting C8, C11 and C24 and VCORE pin 37 to the power rail such that the
caps are closer to the Si468x VCORE pin than the via. Route C8, C11 and C24 only to DBYP directly with a short
(6-mil width) low inductance trace.
C5 (1uF) is an
optional
bypass capacitor for DACREF pin 17 if customer uses analog audio output. Place C4 as
close as possible to DACREF pin. Customers do not need to populate this capacitor if they are using digital audio
output only.
C20 and C21 (1uF) are
optional
ac coupling capacitors for analog audio outputs. The value should be selected to
work well with the customer’s choice of audio amp.
X1 is an
optional
crystal required only when using the internal oscillator feature. Place the crystal X1 as close to
XTALI (pin 15) and XTALO (pin 16) as possible to minimize current loops.
3.3. Layout Guide
The following placement/layout guidelines are suggested for 4-layer PCB:
PCB
layer assignment:
Layer 1 top side placement and routing for RF and analog traces
Layer 2 ground plane
Layer 3 routing for high frequency digital traces and ground plane
Layer 4 bottom side placement and routing for low frequency digital traces
Minimum 6-mil trace
Minimum 6-mil trace spacing
6-mil drill 9-mil plating for normal vias
Minimum 10-mil component spacing
Power routed by trace
0402 component size or larger
4
Rev. 0.2
AN851
1
2
1
6
4
3
2
1
2
1
2
1
2
5
7
3
1
4
6
5
3
5
1
1
2
2
1
2
1
1
2
2
1
2
3
4
5
6
7
8
1
1
1
1
1
2
1
2
1
2
1
2
1
2
2
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
2
4
3
5
2
1
2
2
1
2
1
1
2
1
2
1
2
2
3
9
10
11
12
13
14
49
15
16
17
18
19
20
21
22
23
30
29
28
27
26
25
24
2
2
1
2
1
1
2
1
1
2
1
1
1
2
4
1
3
2
2
2
1
1
2
1
2
4
1
Figure 2. Si468x QFN Layout Design with Legend
Figure 2 shows Si468x layout with all 4 layers and crystal support. All bypass components are placed around the
silicon as close as possible. A few things to note:
The
lowest value capacitor (8.2 pF) shall be placed the closest to the chip.
Crystal and Audio traces shall be short in length and the recommended trace width is 6 mils.
To minimize the loop area, all return currents shall be returned to its source as compactly as possible.
Rev. 0.2
5
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