AN349
Si4708/09 P
ROGRAMMING
G
U I D E
1. Introduction
1.1. Scope
This document applies to Si4708/09 and example code version 0.1 and greater. Refer to www.mysilabs.com for
example code.
1.2. Purpose
This document is intended to be used with Silicon Laboratories “AN230: Si4700/01/02/03 Programming Guide."
The purpose of this programming guide is to describe features that are unique to the Si4708/09:
Device initialization sequence and busmode selection
Powerup and powerdown sequences
Hardware control registers
For topics that are not covered in this document, refer to AN230.
This document references the Si4708/09 data sheet and AN230.
1.3. Terminology
SENB or SEN—serial enable pin, active low, used only for 3-wire operation.
SDIO—serial data in/data out pin.
SCLK—serial clock pin.
RSTB or RST—reset pin, active low.
Device—refers to the Si4708/09.
1.4. Differences between Si4708/09 and Si4700/01/02/03
The Si4708/09 uses a 2.5x2.5 mm 16-pin QFN package. The Si4702/03 and Si4700/01 use 20-pin and 24-pin
packages, respectively. For the purpose of programming, the key difference is that the Si4708/09 does not have
GPIO1 and GPIO3 pins, and, as a result, the Si4708/09 does not offer an internal oscillator function and only offers
bus mode selection with the SENB pin. This necessitates minor differences in the initialization sequence, busmode
selection, powerup and powerdown sequences, and hardware control registers for the Si4708/09. Key differences
between the Si4708/09 and the Si4700/01/02/03 are presented in bold text.
Rev. 0.1 7/08
Copyright © 2008 by Silicon Laboratories
AN349
AN349
T
ABLE
OF
C
ONTENTS
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.1. Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.2. Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.3. Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.4. Differences between Si4708/09 and Si4700/01/02/03 . . . . . . . . . . . . . . . . . . . . . . . .1
2. Hardware Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2.1. Power, Initialization Sequence, and Busmode Selection . . . . . . . . . . . . . . . . . . . . . .4
2.2. 2-Wire Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
3. Software Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3.1. Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3.2. Hardware Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3.3. General Configuration Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.4. Regional Configuration Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.5. End User Adjustable Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.6. Seek Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.7. Tune Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.8. RDS/RBDS (Si4709 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4. Programming with Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5. Command and Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Appendix—Seek Adjustability and Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Rev. 0.1
3
AN349
2. Hardware Description
2.1. Power, Initialization Sequence, and Busmode Selection
VA,VD Supply
VIO Supply
RST Pin
RCLK Pin
ENABLE Bit
1
2
3
4
5
Figure 1. Initialization Sequence
2.1.1. Hardware Initialization
The FM tuner device is capable of communicating using either a 3-wire or 2-wire interface. The selection of this
interface is made during the reset sequence.
Figure 1 demonstrates the sequencing of hardware events relative to reset. Figure 2 combines this information
with the setting of the ENABLE and DISABLE bits to better describe the possible combinations. The following steps
should be used to initialize the device properly.
1. Supply VA and VD.
2. Supply VIO while keeping the RST pin low. Note that power supplies may be sequenced in any order (steps 1
and 2 may be reversed).
3. Configure the SENB pin for bus mode selection. See Figure 3, “Powerup, Powerdown, and Reset Flowchart,”
on page 6.
4. Set the RST pin high. The device registers may now be read and written.
5. Provide RCLK. A delay may be necessary for some external oscillator circuits to ensure that the
oscillator has stabilized. Please determine the necessary stabilization time for the clock source in the
system.
Note:
The Si4708/09 does not offer an internal oscillator option.
6. Set the ENABLE bit high and the DISABLE bit low to power up the device.
2.1.2. Hardware Powerdown
A powerdown mode is available to reduce power consumption when the part is idle. Setting both the ENABLE bit
high and the DISABLE bit high starts the powerdown sequence. This disables analog and digital circuitry while
maintaining register configuration and keeping the bus active. Note that the device automatically sets the ENABLE
bit low after the internal powerdown sequence completes. Setting the ENABLE bit low directly will cause the device
to partially powerdown and should be avoided. See Figure 2. Setting the ENABLE bit high and the DISABLE bit low
will bring the device out of powerdown mode and resume normal operation. Refer to Figure 1 for more information.
To power down the device:
1. Set Register 4 [5:4], [3:2], and [1:0] to 0b10. This step is required for the Si4708/09 to ensure VIO
powerdown mode current meets data sheet specifications.
2. Set the ENABLE bit high and the DISABLE bit high to place the device in powerdown mode. Note that all
register states are maintained so long as VIO is supplied and the RST pin is high.
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Rev. 0.1
AN349
3. Remove VA and VD supplies as needed.
To power up the device (after power down):
Note:
VIO is still supplied in this scenario. If VIO is not supplied, refer to 2.1.1. "Hardware Initialization”
1. Supply VA and VD.
2. Set the ENABLE bit high and the DISABLE bit low to powerup the device.
Setting the RST pin low will disable analog and digital circuitry, reset the registers to their default settings, and
disable the bus. Setting the RST pin high will bring the device out of reset, place the device in powerdown mode,
and latch which bus mode will be used to communicate with the device. The bus mode selection is determined by
the SENB pin. To select 2-wire operation, the SENB pin must be sampled high by the device on the rising edge of
RST. To select 3-wire operation, the SENB pin must be sampled low by the device on the rising edge of RST (See
Figure 3). Please refer to the data sheet for more information regarding bus selection and timing requirements of
the RST signal.
More details on the register access during powerup and powerdown can be found in Section "3.2.1.ENABLE
(02h.0)/DISABLE (02h.6)—Powerup Control" on page 8.
Device Status
Low power,
Inactive
Inactive
Registers reset to
default values
Bus Inactive
RST = GND
Power Supply Status
VA Optional
VD Optional
VIO Optional
RCLK Optional
VIO must be supplied prior to the
rising edge of reset
Low power,
Bus Accessible
RST = VIO
Powerdown
Write:
ENABLE = 1
DISABLE = 1
Read:
ENABLE = 0
DISABLE = 0
VA Optional
VD Optional
VIO Required
RCLK Optional
VA, VD, and RCLK must be supplied
prior to writing ENABLE = 1
Normal
Operation
Powerup
Write:
ENABLE = 1
DISABLE = 0
Read:
ENABLE = 1
DISABLE = 0
Write:
ENABLE = 1
DISABLE = 0
VA Required
VD Required
VIO Required
RCLK Required
Undesirable,
Do Not Use
Partial
Powerdown
Read:
ENABLE = 0
DISABLE = X
Write:
ENABLE = 0
DISABLE = X
VA Optional
VD Optional
VIO Required
RCLK Optional
Note:
See data sheet for further details.
Figure 2. Powerup, Powerdown, and Reset State Diagram
Rev. 0.1
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