NVMFS5C645NL
Power MOSFET
Features
60 V, 4.0 mW, 100 A, Single N−Channel
•
•
•
•
Small Footprint (5x6 mm) for Compact Design
Low R
DS(on)
to Minimize Conduction Losses
Low Q
G
and Capacitance to Minimize Driver Losses
NVMFS5C645NLWF
−
Wettable Flank Option for Enhanced Optical
Inspection
•
AEC−Q101 Qualified and PPAP Capable
•
These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS
(T
J
= 25°C unless otherwise noted)
Parameter
Drain−to−Source Voltage
Gate−to−Source Voltage
Continuous Drain
Current R
qJC
(Notes 1, 3)
Power Dissipation
R
qJC
(Note 1)
Continuous Drain
Current R
qJA
(Notes 1, 2, 3)
Power Dissipation
R
qJA
(Notes 1 & 2)
Pulsed Drain Current
T
C
= 25°C
Steady
State
T
C
= 100°C
T
C
= 25°C
T
C
= 100°C
T
A
= 25°C
Steady
State
T
A
= 100°C
T
A
= 25°C
T
A
= 100°C
T
A
= 25°C, t
p
= 10
ms
I
DM
T
J
, T
stg
I
S
E
AS
T
L
P
D
I
D
P
D
Symbol
V
DSS
V
GS
I
D
Value
60
±20
100
71
79
40
22
15
3.7
1.8
820
−55
to
+175
100
185
260
A
°C
A
mJ
°C
W
1
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V
(BR)DSS
60 V
R
DS(ON)
MAX
4.0 mW @ 10 V
5.7 mW @ 4.5 V
I
D
MAX
100 A
Unit
V
V
A
G (4)
D (5)
W
S (1,2,3)
N−CHANNEL MOSFET
A
MARKING
DIAGRAM
D
S
S
S
G
D
5C645L
AYWZZ
D
D
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Lot Traceability
Operating Junction and Storage Temperature
Source Current (Body Diode)
Single Pulse Drain−to−Source Avalanche
Energy (I
L(pk)
= 5 A)
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
DFN5
(SO−8FL)
CASE 488AA
STYLE 1
5C645L
A
Y
W
ZZ
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter
Junction−to−Case
−
Steady State
Junction−to−Ambient
−
Steady State (Note 2)
Symbol
R
qJC
R
qJA
Value
1.9
41
Unit
°C/W
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 5 of this data sheet.
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Surface−mounted on FR4 board using a 650 mm
2
, 2 oz. Cu pad.
3. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
©
Semiconductor Components Industries, LLC, 2016
March, 2018
−
Rev. 3
1
Publication Order Number:
NVMFS5C645NL/D
NVMFS5C645NL
ELECTRICAL CHARACTERISTICS
(T
J
= 25°C unless otherwise specified)
Parameter
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
Drain−to−Source Breakdown Voltage
Temperature Coefficient
Zero Gate Voltage Drain Current
V
(BR)DSS
V
(BR)DSS
/
T
J
I
DSS
I
GSS
V
GS(TH)
V
GS(TH)
/T
J
R
DS(on)
g
FS
C
ISS
C
OSS
C
RSS
Q
G(TOT)
Q
G(TOT)
Q
G(TH)
Q
GS
Q
GD
V
GP
t
d(ON)
t
r
t
d(OFF)
t
f
V
SD
t
RR
t
a
t
b
Q
RR
V
GS
= 0 V, dI
S
/dt = 100 A/ms,
I
S
= 50 A
T
J
= 25°C
T
J
= 125°C
V
GS
= 4.5 V, V
DS
= 30 V,
I
D
= 50 A, R
G
= 2.5
W
V
GS
= 4.5 V, V
DS
= 30 V; I
D
= 50 A
V
GS
= 4.5 V, V
DS
= 30 V; I
D
= 50 A
V
GS
= 10 V, V
DS
= 30 V; I
D
= 50 A
V
GS
= 0 V, f = 1 MHz, V
DS
= 50 V
V
GS
= 10 V
V
GS
= 4.5 V
Forward Transconductance
CHARGES, CAPACITANCES & GATE RESISTANCE
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge
Total Gate Charge
Threshold Gate Charge
Gate−to−Source Charge
Gate−to−Drain Charge
Plateau Voltage
SWITCHING CHARACTERISTICS
(Note 5)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
V
GS
= 0 V,
I
S
= 50 A
0.88
0.78
41
21
20
32
nC
ns
1.2
V
10
15
24
5.0
ns
2200
900
17
16
34
1.5
5.6
5.1
2.8
V
nC
pF
I
D
= 50 A
I
D
= 50 A
V
GS
= 0 V,
V
DS
= 48 V
T
J
= 25
°C
T
J
= 125°C
V
GS
= 0 V, I
D
= 250
mA
60
15.5
10
250
100
V
mV/°C
mA
nA
Symbol
Test Condition
Min
Typ
Max
Unit
Gate−to−Source Leakage Current
ON CHARACTERISTICS
(Note 4)
Gate Threshold Voltage
Threshold Temperature Coefficient
Drain−to−Source On Resistance
V
DS
= 0 V, V
GS
= 20 V
V
GS
= V
DS
, I
D
= 80
mA
1.2
−4.9
3.3
4.6
105
2.0
V
mV/°C
4.0
5.7
mW
S
V
DS
= 15 V, I
D
= 50 A
Reverse Recovery Time
Charge Time
Discharge Time
Reverse Recovery Charge
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Pulse Test: pulse width
v
300
ms,
duty cycle
v
2%.
5. Switching characteristics are independent of operating junction temperatures.
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2
NVMFS5C645NL
TYPICAL CHARACTERISTICS
I
D
, DRAIN CURRENT (A)
I
D
, DRAIN CURRENT (A)
140 10 V to
4.5 V
120
100
80
60
40
20
0
0
0.5
1.0
1.5
3.8 V
3.6 V
3.4 V
3.2 V
3.0 V
2.8 V
140
120
100
80
60
40
20
T
J
=
−55°C
T
J
= 125°C
T
J
= 25°C
2.0
2.5
3.0
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
R
DS(on)
, DRAIN−TO−SOURCE RESISTANCE (W)
R
DS(on)
, DRAIN−TO−SOURCE RESISTANCE (W)
10
9
8
7
6
5
4
3
3
4
5
6
7
8
9
10
T
J
= 25°C
I
D
= 50 A
8
Figure 2. Transfer Characteristics
T
J
= 25°C
7
6
5
4
3
2
V
GS
= 4.5 V
V
GS
= 10 V
10
30
50
70
90
110
130
150
V
GS
, GATE VOLTAGE (V)
I
D
, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
2.5
R
DS(on)
, NORMALIZED DRAIN−TO−
SOURCE RESISTANCE
2.0
1.5
1.0
0.5
0
−50 −25
V
GS
= 10 V
I
D
= 50 A
100,000
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
T
J
= 125°C
I
DSS
, LEAKAGE (nA)
10,000
T
J
= 85°C
1000
100
0
25
50
75
100
125
150
175
10
5
15
25
35
45
55
T
J
, JUNCTION TEMPERATURE (°C)
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
NVMFS5C645NL
TYPICAL CHARACTERISTICS
2400
C, CAPACITANCE (pF)
2000
1600
1200
800
400
0
C
ISS
Q
T
8
6
25
20
15
C
OSS
V
GS
= 0 V
T
J
= 25°C
f = 1 MHz
4
2
0
Q
GS
Q
GD
V
DS
= 30 V
T
J
= 25°C
I
D
= 25 A
10
5
0
C
RSS
0
10
20
30
40
50
60
0
4
8
12
16
20
24
28
32
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Q
G
, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation
1000
I
S
, SOURCE CURRENT (A)
V
GS
= 4.5 V
V
DD
= 30 V
I
D
= 25 A
t, TIME (ns)
100
45
t
d(off)
t
f
t
r
t
d(on)
40
35
30
25
20
15
10
5
1
1
10
R
G
, GATE RESISTANCE (W)
100
0
0.3
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
T
J
= 125°C
T
J
= 25°C
T
J
=
−55°C
10
0.4
0.5
0.6
0.7
0.8
0.9
1.0
V
SD
, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
1000
T
C
= 25°C
V
GS
≤
10 V
100
I
DS
(A)
0.01 ms
0.1 ms
1 ms
10
R
DS(on)
Limit
Thermal Limit
Package Limit
1
0.1
1
V
DS
(V)
10
100
0.1
10 ms
I
PEAK
(A)
10
100
Figure 10. Diode Forward Voltage vs. Current
T
J(initial)
= 25°C
T
J(initial)
= 100°C
1
1E−04
1E−03
TIME IN AVALANCHE (s)
1E−02
Figure 11. Safe Operating Area
Figure 12. I
PEAK
vs. Time in Avalanche
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4
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
10
30
NVMFS5C645NL
100
50% Duty Cycle
10
R
qJA
(t) (°C/W)
20%
10%
5%
2%
1%
NVMFS5C646NL 650 mm
2
, 2 oz., Cu Single Layer Pad
1
0.1
Single Pulse
0.01
0.000001
0.00001
0.0001
0.001
0.01
PULSE TIME (sec)
0.1
1
10
100
1000
Figure 13. Thermal Characteristics
DEVICE ORDERING INFORMATION
Device
NVMFS5C645NLT1G
NVMFS5C645NLWFT1G
NVMFS5C645NLT3G
NVMFS5C645NLWFT3G
NVMFS5C645NLAFT1G
NVMFS5C645NLWFAFT1G
Marking
5C645L
645LWF
5C645L
645LWF
5C645L
645LWF
Package
DFN5
(Pb−Free)
DFN5
(Pb−Free, Wettable Flanks)
DFN5
(Pb−Free)
DFN5
(Pb−Free, Wettable Flanks)
DFN5
(Pb−Free)
DFN5
(Pb−Free, Wettable Flanks)
Shipping
†
1500 / Tape & Reel
1500 / Tape & Reel
5000 / Tape & Reel
5000 / Tape & Reel
1500 / Tape & Reel
1500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
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