N
SFH6315
SFH6316
SFH6343
HIGH SPEED OPTOCOUPLER
Package Dimensions in Inches (mm)
SFH6315/6
NC
1
A
2
8
V
CC
7
Base V
B
6
C
5
E
FEATURES
• Surface Mountable
• Industry Standard SOIC-8 Footprint
• Compatible with Infrared Vapor Phase Reflow and
Wave Soldering Processes
• Isolation Voltage, 2500 V
RMS
• Very High Common Mode Transient Immunity:
15000 V/
µ
s at V
CM
=1500 V Guaranteed (SFH6343)
• High Speed: 1 Mb/s
• TTL Compatible
• Guaranteed AC and DC Performance Over
Temperature: 0
°
C to 70
°
C
• Open Collector Output
• Pin Compatible with HP Optocouplers
SFH6315—HCPL0500
SFH6316—HCPL0501
SFH6343—HCPL0453
APPLICATIONS
• Line Receivers
• Logic Ground Isolation
• Analog Signal Ground Isolation
• Replace Pulse Transformers
EW
.120±.002
(3.05±.05)
.240
(6.10)
Pin 1
.192±.005
(4.88±.13)
.004 (.10)
.008 (.20)
.050 (1.27) typ.
.021 (.53)
.020±.004
(.15±.10)
2 plcs.
K
3
NC
4
SFH6343
C .154±.002
L
(3.91±.05)
.016
(.41)
NC
1
A
2
K
3
NC
4
8
V
CC
7
NC
6
C
5
E
.015±.002
(.38±.05)
40°
7°
.058±.005
(1.49±.13)
.125±.005
(3.18±.13)
Lead
Coplanarity
±.0015
(.04)
max.
.008 (.20)
5° max.
R.010
(.25) max.
TOLERANCE:
±
.005 (unless otherwise noted)
DESCRIPTION
The SFH6315/16/43, high speed optocouplers, each
consists of a GaAlAs infrared emitting diode, optically
coupled with an integrated photodetector and a high
speed transistor. The photodetector is junction isolated
from the transistor to reduce miller capacitance effects.
The open collector output function allows circuit design-
ers to adjust the load conditions when interfacing with
different logic systems such as TTL, CMOS, etc.
Because the SFH6343 has a Faraday shield on the
detector chip, it can also reject and minimize high input
to output common mode transient voltages. There is no
base connection, further reducing the potential electrical
noise entering the package.
The SFH6315/16/43 are packaged in industry standard
SOIC-8 packages and are suitable for surface mounting.
Absolute Maximum Ratings
Emitter (GaAlAs)
Reverse Voltage........................................................... 3 V
DC Forward Current................................................25 mA
Surge Forward Current ................................................1 A
tp
≤
1
µ
s, 300 pulses/sec.
Total Power Dissipation (T
A
≤
70
°
C)......................... 45 mW
Absolute Maximum Ratings
(continued)
Detector(Si Photodiode + Transistor)
Supply Voltage ............................................................–0.5 to 30 V
Output Voltage ..........................................................–0.5 to
≥
20 V
Output Current....................................................................... 8 mA
Total Power Dissipation (T
A
≤
70
°
C) ................................... 100 mW
Package
Isolation Test Voltage
between emitter and detector ..............................2500 VAC
RMS
(refer to climate DIN 40046, part 2, Nov. 74)
Pollution Degree (DIN VDE0110) .................................................2
Creepage ............................................................................
≥
4 mm
Clearance............................................................................
≥
4 mm
Comparative Tracking Index
per DIN IEC 112/VDE 0303, part 1 .......................................175
Isolation Resistance
V
IO
=500 V, T
A
=25
°
C, R
ISOL
(Note 2)..............................
≥
10
12
Ω
V
IO
=500 V, T
A
=100
°
C, R
ISOL
(Note 2).............................
≥
10
11
Ω
Storage Temperature Range .............................. –55
°
C to +150
°
C
Ambient Temperature Range ............................. –55
°
C to +100
°
C
Junction Temperature...........................................................100
°
C
Soldering Temperature (t=10 sec. max.)..............................260
°
C
Dip soldering: distance to seating plane
≥
1.5 mm
Specifications subject to change.
1
Switching Specifications
Over recommended temperature (T
A
=0
°
C to 70
°
C), V
CC
=5 V, I
F
=16 mA unless otherwise specified. *All typical values, T
A
=25°C
Parameter
Propagation Delay Time
to Logic Low at Output
Sym-
bol
t
PHL
Device
SFH6315
Min.
Typ.*
0.5
Max.
1.5
2.0
SFH6316
SFH6343
Propagation Delay Time
to Logic High at Output
t
PLH
SFH6315
0.25
0.8
1.0
0.5
1.5
2.0
SFH6316
SFH6343
Common Mode Transient
Immunity at Logic High Level
Output
|CM
H
|
SFH6315
SFH6316
SFH6343
15
0.5
0.8
1.0
1
1
30
kV/µs
R
L
=4.1 KΩ
R
L
=1.9 KΩ
R
L
=1.9 KΩ
I
F
=0 mA
T
A
=25°C
V
CM
=10 V
P-P
2
I
F
=0 mA
T
A
=25°C
V
CM
=1500 V
P-P
I
F
=16 mA
T
A
=25°C
V
CM
=10 V
P-P
2
SFH6343
15
30
R
L
=1.9 KΩ
I
F
=16 mA
T
A
=25°C
V
CM
=1500 V
P-P
3, 4, 5
3, 4, 5
µs
T
A
=25°C
T
A
=25°C
R
L
=4.1 KΩ
R
L
=1.9 KΩ
1
4, 5
µs
T
A
=25°C
R
L
=1.9 KΩ
Units
Test Conditions
T
A
=25°C
R
L
=4.1 KΩ
1
4, 5
Fig.
Note
Common Mode Transient
Immunity at Logic Low Level
Output
|CM
L
|
SFH6315
SFH6316
1
1
kV/µs
R
L
=4.1 KΩ
R
L
=1.9 KΩ
Notes
1.
Current transfer ratio in percent equals the ratio of output collector current (I
O
) to the forward LED input current (I
F
) times 100.
2.
Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together.
3.
Common mode transient immunity in a Logic High level is the maximum tolerable (positive) dV
cm
/dt on the leading edge of the com-
mon mode pulse (V
CM
) to assure that the output will remain in a Logic High state (i.e., V
O
>2.0 V). Common mode transient immunity in
a Logic Low level is the maximum tolerable (negative) dVcm/dt on the trailing edge of the common mode pulse signal (V
CM
to assure
that the output will remain in a Logic Low state (i.e., V
O
<0.8 V).
4.
The 1.9 KΩ load represents 1 TTL unit load of 1.6 mA and the 5.6 kΩ pull-up resistor.
5.
The 4.1 KΩ load represents 1 LSTTL unit load of 0.36 mA and the 6.1 kΩ pull-up resistor.
6.
A 0.1
µf
bypass capacitor connected between pins 5 and 8 is recommended.
Figure 2. Test circuit for transient immunity and typical waveforms
V
CM
0 V 10%
90%
tr
90%
10%
tf
A
1
I
F
8
7
6
0.1
µF
R
L
+5 V
2
3
4
V
FF
+
V
CM
–
V
O
V
O
Switch at A: IF=0 mA
5V
B
5
V
O
Switch at B: IF=16 mA
V
OL
Pulse Generator
SFH6315/6316/6343
3
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