Advanced Power MOSFET
FEATURES
!
Avalanche Rugged Technology
!
Rugged Gate Oxide Technology
!
Lower Input Capacitance
!
Improved Gate Charge
!
Extended Safe Operating Area
!
Lower Leakage Current : 10
µA
(Max.) @ V
DS
= -250V
!
Lower R
DS(ON)
: 0.549
Ω
(Typ.)
SFH9244
BV
DSS
= -250 V
R
DS(on)
= 0.8
Ω
I
D
= -8.7 A
TO-3P
1
2
3
1.Gate 2. Drain 3. Source
Absolute Maximum Ratings
Symbol
V
DSS
I
D
I
DM
V
GS
E
AS
I
AR
E
AR
dv/dt
P
D
T
J
, T
STG
T
L
Characteristic
Drain-to-Source Voltage
Continuous Drain Current (T
C
=25 C)
Continuous Drain Current (T
C
=100 C)
Drain Current-Pulsed
Gate-to-Source Voltage
Single Pulsed Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Total Power Dissipation (T
C
=25 C)
Linear Derating Factor
Operating Junction and
Storage Temperature Range
Maximum Lead Temp. for Soldering
Purposes, 1/8 “ from case for 5-seconds
o
2
O
1
O
1
O
3
O
o
o
Value
-250
-8.7
-6.0
1
O
Units
V
A
A
V
mJ
A
mJ
V/ns
W
W/ C
o
-35
+ 30
_
473
-8.7
12.6
-4.8
126
1.0
- 55 to +150
o
C
300
Thermal Resistance
Symbol
R
θJC
R
θCS
R
θJA
Characteristic
Junction-to-Case
Case-to-Sink
Junction-to-Ambient
Typ.
--
0.24
--
Max.
1.0
--
40
o
Units
C/W
Rev. A
SFH9244
Electrical Characteristics
(T
C
=25
o
C unless otherwise specified)
Symbol
BV
DSS
∆BV/∆T
J
V
GS(th)
I
GSS
I
DSS
R
DS(on)
g
fs
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
Q
g
Q
gs
Q
gd
Characteristic
Drain-Source Breakdown Voltage
Breakdown Voltage Temp. Coeff.
Gate Threshold Voltage
Gate-Source Leakage , Forward
Gate-Source Leakage , Reverse
Drain-to-Source Leakage Current
Static Drain-Source
On-State Resistance
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain(“Miller”) Charge
Min. Typ. Max. Units
-250
--
-2.0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
-0.22
--
--
--
--
--
--
5.8
175
65
14
21
47
18
45
8.7
23.4
--
--
-4.0
-100
100
-10
-100
0.8
--
265
100
40
50
105
45
58
--
--
nC
ns
µA
Ω
S
pF
V
o
P-CHANNEL
POWER MOSFET
Test Condition
V
GS
=0V,I
D
=-250µA
See Fig 7
V
DS
=-5V,I
D
=-250µA
V
GS
=-30V
V
GS
=30V
V
DS
=-250V
V
DS
=-200V,T
C
=125 C
V
GS
=-10V,I
D
=-4.4A
V
DS
=-40V,I
D
=-4.4A
4
O
4
O
o
V/ C I
D
=-250µA
V
nA
1205 1565
V
GS
=0V,V
DS
=-25V,f =1MHz
See Fig 5
V
DD
=-125V,I
D
=-8.6A,
R
G
=9.1Ω
See Fig 13
4
5
OO
V
DS
=-200V,V
GS
=-10V,
I
D
=-8.6A
See Fig 6 & Fig 12
4
5
OO
Source-Drain Diode Ratings and Characteristics
Symbol
I
S
I
SM
V
SD
t
rr
Q
rr
Characteristic
Continuous Source Current
Pulsed-Source Current
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
1
O
4
O
Min. Typ. Max. Units
--
--
--
--
--
--
--
--
210
1.82
-8.7
-35
-5.0
--
--
A
V
ns
µC
Test Condition
Integral reverse pn-diode
in the MOSFET
T
J
=25 C,I
S
=-8.7A,V
GS
=0V
T
J
=25 C,I
F
=-8.6A
di
F
/dt=100A/µs
4
O
o
o
Notes ;
1
O
Repetitive Rating : Pulse Width Limited by Maximum Junction Temperature
2
O
L=10mH, I
AS
=-8.7A, V
DD
=-50V, R
G
=27Ω
*
, Starting T
J
=25
o
C
_
_
_
3
O
I
SD
<
-8.6A, di/dt
<
450A/µs, V
DD
<
BV
DSS
, Starting T
J
=25
o
C
_
4
O
Pulse Test : Pulse Width = 250µs, Duty Cycle
<
2%
5
O
Essentially Independent of Operating Temperature
P-CHANNEL
POWER MOSFET
Fig 1. Output Characteristics
V
GS
Top :
-1 V
5
-1 V
0
- 8.0 V
- 7.0 V
- 6.0 V
- 5.5 V
- 5.0 V
Bottom : - 4.5 V
SFH9244
Fig 2. Transfer Characteristics
-I
D
, Drain Current [A]
-I
D
, Drain Current [A]
1
1
0
1
1
0
1 0
o
C
5
1
0
0
1
0
0
2
o
C
5
@Nts:
oe
1 2 0
µ
s P l e T s
. 5
us et
2 T = 2
o
C
.
C
5
1
-1 -1
0
1
0
1
0
0
1
1
0
- 5
o
C
5
1
-1
0
2
4
6
@Nts:
oe
1 V =0V
.
GS
2 V =-0V
.
DS
4
3 2 0
µ
s P l e T s
. 5
us et
8
1
0
-V
DS
, Drain-Source Voltage [V]
-V
GS
, Gate-Source Voltage [V]
Fig 3. On-Resistance vs. Drain Current
20
.
Fig 4. Source-Drain Diode Forward Voltage
-I
DR
, Reverse Drain Current [A]
R
DS(on)
, [
Ω
]
Drain-Source On-Resistance
15
.
1
1
0
V =-0V
1
GS
10
.
1
0
0
1 0
o
C
5
2
o
C
5
1
-1
0
05
.
@Nts:
oe
1 V =0V
.
GS
2 2 0
µ
s P l e T s
. 5
us et
20
.
25
.
30
.
35
.
40
.
45
.
05
.
V =-0V
2
GS
00
.
0
7
1
4
2
1
@ N t : T = 2
o
C
oe
J
5
2
8
10
.
15
.
-I
D
, Drain Current [A]
-V
SD
, Source-Drain Voltage [V]
Fig 5. Capacitance vs. Drain-Source Voltage
20
50
C =C +C (C =sotd)
iss gs gd
ds
h r e
C =C +C
oss ds gd
C =C
rss gd
C
iss
10
50
C
oss
10
00
C
rss
50
0
@Nts:
oe
1 V =0V
.
GS
2 f=1Mz
.
H
Fig 6. Gate Charge vs. Gate-Source Voltage
V =-0V
5
DS
V =-2 V
15
DS
V =-0 V
20
DS
-V
GS
, Gate-Source Voltage [V]
20
00
1
0
Capacitance [pF]
5
@Nts:I =86A
oe
D
-.
0
0
1
0
2
0
3
0
4
0
5
0
0
0
1
0
1
1
0
-V
DS
, Drain-Source Voltage [V]
Q
G
, Total Gate Charge [nC]
SFH9244
Fig 7. Breakdown Voltage vs. Temperature
12
.
P-CHANNEL
POWER MOSFET
Fig 8. On-Resistance vs. Temperature
-BV
DSS
, (Normalized)
Drain-Source Breakdown Voltage
11
.
10
.
-I
D
, Drain Current [A]
1
1
0
1 0
o
C
5
1
0
0
2
o
C
5
09
.
@Nts:
oe
1 V =0V
.
GS
2 I = - 5
µ
A
.
D
20
-0
5
-5
2
0
2
5
5
0
7
5
10
0
15
2
10
5
15
7
- 5
o
C
5
1
-1
0
2
4
6
@Nts:
oe
1 V =0V
.
GS
2 V =-0V
.
DS
4
3 2 0
µ
s P l e T s
. 5
us et
8
1
0
08
.
-5
7
T
J
, Junction Temperature [
o
C]
-V
GS
, Gate-Source Voltage [V]
Fig 9. Max. Safe Operating Area
1
2
0
Oeaini Ti Ae
prto n hs ra
i L m t d b R
DS(on)
s iie y
Fig 10. Max. Drain Current vs. Case Temperature
1
0
-I
D
, Drain Current [A]
-I
D
, Drain Current [A]
8
01m
. s
1
1
0
1 m
0 s
D
C
1
0
0
@Nts:
oe
1 T = 2
o
C
.
C
5
2 T = 1 0
o
C
.
J
5
3 Snl Ple
. ige us
1
-1 0
0
1
0
1m
s
6
4
2
1
1
0
1
2
0
0
2
5
5
0
7
5
10
0
o
15
2
10
5
-V
DS
, Drain-Source Voltage [V]
T
c
, Case Temperature [ C]
Fig 11. Thermal Response
Thermal Response
10
0
D=0.5
@ Notes :
1. Z
θ
J C
(t)=1.0
o
C/W Max.
2. Duty Factor, D=t
1
/t
2
3. T
J M
-T
C
=P
D M
*Z
θ
J C
(t)
P
.
DM
0.2
10
- 1
0.1
0.05
0.02
0.01
single pulse
Z (t) ,
θ
JC
t
1.
t
2.
10
- 2 - 5
10
10
- 4
10
- 3
10
- 2
10
- 1
10
0
10
1
t
1
, Square Wave Pulse Duration
[sec]
P-CHANNEL
POWER MOSFET
Fig 12. Gate Charge Test Circuit & Waveform
SFH9244
“ Current Regulator ”
50KΩ
12V
200nF
300nF
Same Type
as DUT
V
GS
Q
g
-10V
V
DS
V
GS
DUT
-3mA
Q
gs
Q
gd
R
1
Current Sampling (I
G
)
Resistor
R
2
Current Sampling (I
D
)
Resistor
Charge
Fig 13. Resistive Switching Test Circuit & Waveforms
R
L
V
out
V
in
R
G
DUT
-10V
V
out
90%
t
on
t
off
t
r
t
d(off)
t
f
V
DD
( 0.5 rated V
DS
)
t
d(on)
V
in
10%
Fig 14. Unclamped Inductive Switching Test Circuit & Waveforms
L
L
V
DS
Vary t
p
to obtain
required peak I
D
BV
DSS
1
E
AS
= ---- L
L
I
AS2
--------------------
2
BV
DSS
-- V
DD
t
p
I
D
V
DD
Time
V
DS
(t)
R
G
DUT
-10V
t
p
C
V
DD
I
AS
BV
DSS
I
D
(t)
FPGA/CPLD
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