Ordering number : ENA1645B
LV8112V
Bi-CMOS IC
For Polygon Mirror Motor
http://onsemi.com
3-phase Brushless Motor Driver
Overview
The LV8112V is a 3-phase brushless motor driver for polygon mirror motor driving of LBP.
A circuit needed to drive of polygon mirror motor can be composed of a single-chip. Also, the output transistor is made
DMOS by using BiDC process, and by adopting the synchronous rectification method, the lower power consumption
(Heat generation) is achieved.
Features
•
3-phase bipolar drive
•
Direct PWM drive + synchronous rectification
•
IO max1 = 2.5A
•
IO max1 = 3.0A (t
≤
0.1ms)
•
Output current control circuit
•
PLL speed control circuit
•
Phase lock detection output (with mask function)
•
Compatible with Hall FG
•
Provides a 5V regulator output
Specifications
Absolute Maximum Ratings
at Ta = 25°C
Parameter
Supply voltage
Symbol
VCC max
VG max
Output current
IO max1
IO max2
Allowable Power dissipation
Operation temperature
Storage temperature
Junction temperature
Pd max
Topr
Tstg
Tj max
VCC pin
VG pin
*1
t
≤
0.1ms *1
•
Full complement of on-chip protection circuits, including lock
protection, current limiter, under-voltage protection, and thermal
shutdown protection circuits
•
Circuit to switch slowing down method while stopped
(Free run or Short-circuit brake)
•
Constraint protection detection signal switching circuit (FG or LD)
•
Forward / Reverse switching circuit
•
Hall bias pin (Bias current cut in a stopped state)
•
SDCC (Speed Detection Current Control) function
Conditions
Ratings
37
42
2.5
3.0
1.7
-25 to +80
-55 to +150
150
Unit
V
V
A
A
W
°C
°C
°C
Mounted on a specified board *2
*1. Tj max = 150°C must not be exceeded.
*2. Specified board: 114.3mm × 76.1mm × 1.6mm, glass epoxy board.
Caution 1) Absolute maximum ratings represent the value which cannot be exceeded for any length of time.
Caution 2) Even when the device is used within the range of absolute maximum ratings, as a result of continuous usage under high temperature, high current,
high voltage, or drastic temperature change, the reliability of the IC may be degraded. Please contact us for the further details.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Semiconductor Components Industries, LLC, 2013
May, 2013
31412 SY 20120224-S00005 / 30310 SY / 11310 SY 20091224-S00004 No.A1645-1/13
LV8112V
Allowable Operating Ranges
at Ta = 25°C
Parameter
Supply voltage range
5V constant voltage output current
LD pin applied voltage
LD pin output current
FG pin applied voltage
FG pin output current
HB pin output current
Symbol
VCC
IREG
VLD
ILD
VFG
IFG
IHB
Conditions
Ratings
10 to 35
0 to -30
0 to 5
0 to 15
0 to 5
0 to 15
0 to -30
Unit
V
mA
V
mA
V
mA
mA
Electrical Characteristics
at Ta
=
25°C, VCC = 24V
Parameter
Current drain
Symbol
ICC1
ICC2
5V Constant Voltage Output
Output voltage
Line regulation
Load regulation
Temperature coefficient
Output Block
Output ON resistance
Output leakage current
Lower side Diode forward voltage
Upper side Diode forward voltage
Charge Pump Output
(VG pin)
Output voltage
CP1 pin
Output ON resistance (High level)
Output ON resistance (Low level)
Hall Amplifier Block
Input bias current
Common mode input voltage range
Hall input sensitivity
Hysteresis
Input voltage L
→
H
Input voltage H
→
L
Hall Bias
(HB pin) P-channel Output
Output voltage ON resistance
Output leakage current
FG Amplifier Schmitt Block
(IN1)
Input amplifier gain
Input hysteresis (H
→
L)
Input hysteresis (L
→
H)
hysteresis
GFG
VSHL(FGS)
VSLH(FGS)
VFGL
Design target value *
Input referred, Design target value *
Input referred, Design target value *
Input referred, Design target value *
5
0
10
10
times
mV
mV
mV
VOL(HB)
IL(HB)
IHB = -20mA
VO = 0V
20
30
10
Ω
μA
ΔV
IN(HA)
VSLH
VSHL
IHB(HA)
VICM
-2
0.5
80
15
24
12
-12
42
-0.5
VREG-2.0
μA
V
mVp-p
mV
mV
mV
VOH(CP1)
VOL(CP1)
ICP1 = -2mA
ICP1 = 2mA
500
300
700
400
Ω
Ω
VGOUT
VCC+4.9
V
RON
IOleak
VD1
VD2
IO = 1A , Sum of the lower and upper side
outputs
Design target value *
ID = -1A
ID = 1A
1.0
1.0
10
1.35
1.35
μA
V
V
1.5
1.9
Ω
VREG
ΔVREG1
ΔVREG2
ΔVREG3
VCC = 10 to 35V
IO = -5 to -20mA
Design target value *
4.65
5.0
20
25
0
5.35
100
60
V
mV
mV
mV/°C
In a stop state
Conditions
min
Ratings
typ
5.5
1.0
max
6.5
1.5
mA
mA
Unit
* Design target value, Do not measurement.
Continued on next page.
No.A1645-2/13
LV8112V
Continued from preceding page.
Parameter
FGFIL pin
High level output voltage
Low level output voltage
External capacitor charge current
External capacitor discharge current
Amplitude
FG Output
Output ON resistance
Output leakage current
PWM Oscillator
High level output voltage
Low level output voltage
External capacitor charge current
Oscillation frequency
Amplitude
Recommended operation frequency
range
CSD Oscillation Circuit
High level output voltage
Low level output voltage
Amplitude
External capacitor charge current
External Capacitor Discharge Current
Oscillation frequency
Phase comparing output
Output ON resistance (high level)
Output ON resistance (low level)
Phase Lock Detection Output
Output ON resistance
Output leakage current
Error Amplifier Block
Input offset voltage
Input bias current
High level output voltage
Low level output voltage
DC bias level
Current Control Circuit
Drive gain
GDF
While phase locked
0.5
0.55
0.6
times
VIO(ER)
IB(ER)
VOH(ER)
VOL(ER)
VB(ER)
IOH = -100μA
IOL = 100μA
Design target value *
-10
-1
EI+0.7
EI-1.75
-5%
EI+0.85
EI-1.6
VREG/2
+10
+1
EI+1.0
EI-1.45
5%
mV
μA
V
V
V
VOL(LD)
IL(LD)
ILD = 10mA
VO = 5V
20
30
10
Ω
μA
VPDH
VPDL
IOH = -100μA
IOL = 100μA
500
500
700
700
Ω
Ω
VOH(CSD)
VOL(CSD)
V(CSD)
ICHG1(CSD) VCHG1 = 2.0V
ICHG2(CSD) VCHG2 = 2.0V
f(CSD)
C = 0.068μF, Design target value *
2.7
0.8
1.75
-14
8
30
3.0
1.0
2.0
-10
11
40
3.3
1.2
2.25
-6
14
50
V
V
Vp-p
μA
μA
Hz
VOH(PWM)
VOL(PWM)
ICHG(PWM)
f(PWM)
V(PWM)
fOPR
VPWM = 2V
C = 150pF
2.95
1.3
-90
180
1.5
15
3.2
1.5
-70
225
1.7
3.45
1.7
-50
270
1.9
300
V
V
μA
kHz
Vp-p
kHz
VOL(FG)
IL(FG)
IFG = 7mA
VO = 5V
20
30
10
Ω
μA
VOH(FGFIL)
VOL(FGFIL)
ICHG1
ICHG2
V(FGFIL)
VCHG1 = 1.5V
VCHG2 = 1.5V
2.7
0.75
-5
3
1.95
3.0
0.85
-4
4
2.15
3.3
0.95
-3
5
2.35
V
V
μA
μA
Vp-p
Symbol
Conditions
min
Ratings
typ
max
Unit
Current Limiter Circuit
(pins RF and RFS)
Limiter voltage
Under-voltage Protection
Operation voltage
Hyteresis
CLD Circuit
External capacitor charge current
Operation voltage
Thermal Shutdown Operation
Thermal shutdown operation
temperature
Hysteresis
ΔTSD
Design target value (Junction temperature)
30
°C
TSD
Design target value (Junction temperature)
150
175
°C.
ICLD
VH(CLD)
VCLD = 0V
-4.5
3.25
-3.0
3.5
-1.5
3.75
μA
V
VSD
ΔVSD
8.3
0.2
8.7
0.35
9.1
0.5
V
V
VRF
0.465
0.515
0.565
V
* Design target value, Do not measurement.
Continued on next page.
No.A1645-3/13
LV8112V
Continued from preceding page.
Parameter
CLK pin
External input frequency
High level input voltage
Low level input voltage
Input open voltage
Hysteresis
High level input current
Low level input current
CSDSEL pin
High level input voltage
Low level input voltage
Input open voltage
High level input current
Low level input current
S/S pin
High level input voltage
Low level input voltage
Input open voltage
Hysteresis
High level input current
Low level input current
BRSEL pin
High level input voltage
Low level input voltge
Input open voltage
High level input current
Low level input current
F/R pin
High level input voltage
Low level input voltage
Input open voltage
High level input current
Low level input current
VIH(FR)
VIL(FR)
VIO(FR)
IIH(FR)
IIL(FR)
VF/R = VREG
VF/R = 0V
2.0
0
VREG-0.5
-10
-110
0
-85
VREG
1.0
VREG
+10
-60
V
V
V
μA
μA
VIH(BRSEL)
VIL(BRSEL)
VIO(BRSEL)
IIH(BRSEL)
IIL(BRSEL)
VBRSEL = VREG
VBRSEL = 0V
2.0
0
VREG-0.5
-10
-110
0
-85
VREG
1.0
VREG
+10
-60
V
V
V
μA
μA
VIH(SS)
VIL(SS)
VIO(SS)
VIS(SS)
IIH(SS)
IIL(SS)
VS/S = VREG
VS/S =0V
2.0
0
VREG-0.5
0.2
-10
-110
0.3
0
-85
VREG
1.0
VREG
0.4
+10
-60
V
V
V
V
μA
μA
VIH(CSD)
VIL(CSD)
VIO(CSD)
IIH(CSD)
IIL(CSD)
VCSD = VREG
VCSD = 0V
2.0
0
VREG-0.5
-10
-110
0
-85
VREG
1.0
VREG
+10
-60
V
V
V
μA
μA
fI(CLK)
VIH(CLK)
VIL(CLK)
VIO(CLK)
VIS(CLK)
IIH(CLK)
IIL(CLK)
VCLK = VREG
VCLK = 0V
0.1
2.0
0
VREG-0.5
0.2
-10
-110
0.3
0
-85
10
VREG
1.0
VREG
0.4
+10
-60
kHz
V
V
V
V
μA
μA
Symbol
Conditions
min
Ratings
typ
max
Unit
No.A1645-4/13
LV8112V
Package Dimensions
unit : mm (typ)
3333
TOP VIEW
15.0
44
23
SIDE VIEW
BOTTOM VIEW
(4.7)
5.6
7.6
(3.5)
1
(0.68)
0.65
0.22
22
0.2
1.7MAX
SIDE VIEW
0.1 (1.5)
0.5
SANYO : SSOP44K(275mil)
2.0
Pd max -- Ta
Allowable power dissipation, Pd max -- W
1.7
1.5
1.0
0.95
0.5
0
-25
0
25
50
75 80
100
Ambient temperature, Ta -- C
Pin Assignment
GND2
VCC1
VCC2
OUT1
OUT2
OUT3
IN3+
IN2+
IN1+
24
23
21
22
Top view
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
SUB
RFS
CP2
CP1
VG
RF
28
27
26
25
LV8112V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
BRSEL
CSDSEL
FGFIL
S/S
FG
PWM
F/R
EI
VREG
EO
FC
CSD
TOC
PH
CLK
PD
LD
GND
CLD
HB
No.A1645-5/13
嵌入式系统
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