Advanced Power MOSFET
FEATURES
Avalanche Rugged Technology
Rugged Gate Oxide Technology
Lower Input Capacitance
Improved Gate Charge
Extended Safe Operating Area
Lower Leakage Current : 10
µA
(Max.) @ V
DS
= -250V
Low R
DS(ON)
: 0.549
Ω
(Typ.)
1
2
3
SFS9644
BV
DSS
= -250 V
R
DS(on)
= 0.8
Ω
I
D
= -4.9 A
TO-220F
1.Gate 2. Drain 3. Source
Absolute Maximum Ratings
Symbol
V
DSS
I
D
I
DM
V
GS
E
AS
I
AR
E
AR
dv/dt
P
D
T
J
, T
STG
T
L
Characteristic
Drain-to-Source Voltage
Continuous Drain Current (T
C
=25 C)
Continuous Drain Current (T
C
=100 C)
Drain Current-Pulsed
Gate-to-Source Voltage
Single Pulsed Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Total Power Dissipation (T
C
=25 C)
Linear Derating Factor
Operating Junction and
Storage Temperature Range
Maximum Lead Temp. for Soldering
Purposes, 1/8 ” from case for 5-seconds
o
2
O
1
O
1
O
3
O
o
o
Value
-250
-4.9
-3.8
1
O
Units
V
A
A
V
mJ
A
mJ
V/ns
W
W/ C
o
-20
+ 30
_
150
-4.9
4.0
-4.8
40
0.32
- 55 to +150
o
C
300
Thermal Resistance
Symbol
R
θ
JC
R
θ
JA
Characteristic
Junction-to-Case
Junction-to-Ambient
Typ.
--
--
Max.
3.13
62.5
Units
o
C/W
Rev. B
©1999 Fairchild Semiconductor Corporation
SFS9644
Symbol
BV
DSS
∆BV/∆T
J
V
GS(th)
I
GSS
I
DSS
R
DS(on)
g
fs
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
Q
g
Q
gs
Q
gd
Characteristic
Drain-Source Breakdown Voltage
Breakdown Voltage Temp. Coeff.
Gate Threshold Voltage
Gate-Source Leakage , Forward
Gate-Source Leakage , Reverse
Drain-to-Source Leakage Current
Static Drain-Source
On-State Resistance
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain( “ Miller “ ) Charge
Min. Typ. Max. Units
-250
--
-2.0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
-0.22
--
--
--
--
--
--
5.2
175
65
14
21
47
18
45
8.7
23.4
--
--
-4.0
-100
100
-10
-100
0.8
--
265
100
40
50
105
45
58
--
--
nC
ns
µA
Ω
Ω
pF
V
o
P-CHANNEL
POWER MOSFET
Electrical Characteristics
(T
C
=25
o
C unless otherwise specified)
Test Condition
V
GS
=0V,I
D
=-250µA
See Fig 7
V
DS
=-5V,I
D
=-250µA
V
GS
=-30V
V
GS
=30V
V
DS
=-250V
V
DS
=-200V,T
C
=125 C
V
GS
=-10V,I
D
=-2.5A
V
DS
=-40V,I
D
=-2.5A
4
O
4
O
o
V/ C I
D
=-250µA
V
nA
1205 1565
V
GS
=0V,V
DS
=-25V,f =1MHz
See Fig 5
V
DD
=-125V,I
D
=-8.6A,
R
G
=9.1Ω
See Fig 13
4
5
OO
V
DS
=-200V,V
GS
=-10V,
I
D
=-8.6A
See Fig 6 & Fig 12
4
5
OO
Source-Drain Diode Ratings and Characteristics
Symbol
I
S
I
SM
V
SD
t
rr
Q
rr
Characteristic
Continuous Source Current
Pulsed-Source Current
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
1
O
4
O
Min. Typ. Max. Units
--
--
--
--
--
--
--
--
210
1.82
-4.9
-20
-5.0
--
--
A
V
ns
µC
Test Condition
Integral reverse pn-diode
in the MOSFET
T
J
=25 C,I
S
=-4.9A,V
GS
=0V
T
J
=25 C,I
F
=-8.6A
di
F
/dt=100A/µs
4
O
o
o
Notes ;
1
O
Repetitive Rating : Pulse Width Limited by Maximum Junction Temperature
2
O
L=10mH, I
AS
=-4.9A, V
DD
=-50V, R
G
=27Ω
*
, Starting T
J
=25
o
C
_
_
_
3
O
I
SD
<
-8.6A, di/dt
<
450A/µs, V
DD
<
BV
DSS
, Starting T
J
=25
o
C
_
4
O
Pulse Test : Pulse Width = 250
µs,
Duty Cycle
<
2%
5
O
Essentially Independent of Operating Temperature
P-CHANNEL
POWER MOSFET
Fig 1. Output Characteristics
V
GS
SFS9644
Fig 2. Transfer Characteristics
[A]
-I
D
, Drain Current
[A]
1
10
-I
D
, Drain Current
- 15 V
- 10 V
- 8.0 V
- 7.0 V
- 6.0 V
- 5.5 V
- 5.0 V
Bottom : - 4.5 V
Top :
10
1
150
o
C
10
0
25
o
C
@ Notes :
1. V = 0 V
GS
2. V = -40 V
DS
- 55
o
C
3. 250
µ
s Pulse Test
0
10
@ Notes :
1. 250
µ
s Pulse Test
2. T = 25
o
C
C
10
-1
10
-1
10
0
1
10
10
-1
2
4
6
8
10
-V
DS
, Drain-Source Voltage [V]
-V
GS
, Gate-Source Voltage [V]
R
DS(on)
, [ ]
Ω
Drain-Source On-Resistance
Fig 3. On-Resistance vs. Drain Current
2.0
[A]
Fig 4. Source-Drain Diode Forward Voltage
-I
DR
, Reverse Drain Current
10
1
1.5
V = -10 V
GS
1.0
10
0
150
o
C
25
o
C
10
-1
0.5
@ Notes :
1. V = 0 V
GS
2. 250
µ
s Pulse Test
0.5
V = -20 V
GS
0.0
0
7
14
21
28
@ Note : T = 25
o
C
J
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
-I
D
, Drain Current [A]
-V
SD
, Source-Drain Voltage [V]
Fig 5. Capacitance vs. Drain-Source Voltage
C
iss
= C
gs
+ C ( C
ds
= shorted )
gd
C
oss
= C
ds
+ C
gd
Fig 6. Gate Charge vs. Gate-Source Voltage
[V]
2500
[pF]
-V
GS
, Gate-Source Voltage
2000
C
iss
C
rss
= C
gd
10
V
DS
= -50 V
V = -125 V
DS
V
DS
= -200 V
Capacitance
1500
C
oss
1000
C
rss
500
@ Notes :
1. V = 0 V
GS
2. f = 1 MHz
5
@ Notes : I =-8.6 A
D
0
0
10
20
30
40
50
0
10
0
1
10
-V
DS
, Drain-Source Voltage [V]
Q
G
, Total Gate Charge [nC]
SFS9644
Drain-Source Breakdown Voltage
P-CHANNEL
POWER MOSFET
Fig 8. On-Resistance vs. Temperature
[A]
Fig 7. Breakdown Voltage vs. Temperature
1.2
-BV , (Normalized)
DSS
1.0
-I
D
, Drain Current
1.1
10
1
150
o
C
10
0
25
o
C
@ Notes :
1. V = 0 V
GS
2. V = -40 V
DS
- 55
o
C
3. 250
µ
s Pulse Test
0.9
@ Notes :
1. V = 0 V
GS
2. I = -250
µ
A
D
-50
-25
0
25
50
75
100
125
150
175
0.8
-75
10
-1
2
4
6
8
10
T
J
, Junction Temperature [
o
C]
-V
GS
, Gate-Source Voltage [V]
[A]
Fig 9. Max. Safe Operating Area
10
2
Fig 10. Max. Drain Current vs. Case Temperature
6
-I
D
, Drain Current
[A]
-I
D
, Drain Current
0.1 ms
1 ms
10 ms
DC
10
2
Operation in This Area
is Limited by R
DS(on)
5
10
1
4
3
10
0
@ Notes :
1. T = 25
o
C
C
2. T = 150
o
C
J
3. Single Pulse
2
1
10
-1
10
0
10
1
0
25
50
75
100
o
125
150
-V
DS
, Drain-Source Voltage [V]
T
c
, Case Temperature [ C]
Fig 11. Thermal Response
Thermal Response
D=0.5
10
0
0.2
0.1
0.05
10
- 1
0.02
0.01
single pulse
@ Notes :
1. Z
θ
J C
(t)=3.13
C/W Max.
2. Duty Factor, D=t
1
/t
2
3. T
J M
-T
C
=P
D M
*Z
θ
J C
(t)
o
P
.
DM
t
1.
t
2.
Z
θ
JC
(t) ,
10
- 5
10
- 4
10
- 3
10
- 2
10
- 1
10
0
10
1
t
1
, Square Wave Pulse Duration
[sec]
P-CHANNEL
POWER MOSFET
Fig 12. Gate Charge Test Circuit & Waveform
SFS9644
“ Current Regulator ”
50KΩ
12V
200nF
300nF
Same Type
as DUT
V
GS
Q
g
-10V
V
DS
V
GS
DUT
-3mA
Q
gs
Q
gd
R
1
Current Sampling (I
G
)
Resistor
R
2
Current Sampling (I
D
)
Resistor
Charge
Fig 13. Resistive Switching Test Circuit & Waveforms
R
L
V
out
V
in
R
G
DUT
-10V
V
out
90%
t
on
t
off
t
r
t
d(off)
t
f
V
DD
( 0.5 rated V
DS
)
t
d(on)
V
in
10%
Fig 14. Unclamped Inductive Switching Test Circuit & Waveforms
L
L
V
DS
Vary t
p
to obtain
required peak I
D
BV
DSS
1
2
--------------------
E
AS
= ---- L
L
I
AS
2
BV
DSS
-- V
DD
t
p
I
D
V
DD
Time
V
DS
(t)
R
G
DUT
-10V
t
p
C
V
DD
I
D
(t)
I
AS
BV
DSS
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