Advanced Power MOSFET
FEATURES
Avalanche Rugged Technology
Rugged Gate Oxide Technology
Lower Input Capacitance
Improved Gate Charge
Extended Safe Operating Area
Lower Leakage Current : 10
µA
(Max.) @ V
DS
= -200V
Low R
DS(ON)
: 2.084
Ω
(Typ.)
1
SFW/I9610
BV
DSS
= -200 V
R
DS(on)
= 3.0
Ω
I
D
= -1.75 A
D
2
-PAK
2
I
2
-PAK
1
3
2
3
1. Gate 2. Drain 3. Source
Absolute Maximum Ratings
Symbol
V
DSS
I
D
I
DM
V
GS
E
AS
I
AR
E
AR
dv/dt
P
D
Characteristic
Drain-to-Source Voltage
Continuous Drain Current (T
C
=25 C)
Continuous Drain Current (T
C
=100 C)
Drain Current-Pulsed
Gate-to-Source Voltage
Single Pulsed Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Total Power Dissipation (T
A
=25 C) *
Total Power Dissipation (T
C
=25 C)
Linear Derating Factor
T
J
, T
STG
T
L
Operating Junction and
Storage Temperature Range
Maximum Lead Temp. for Soldering
Purposes,
1/8”
from case for 5-seconds
o
o
2
O
1
O
1
O
3
O
o
o
Value
-200
-1.75
-1.0
1
O
Units
V
A
A
V
mJ
A
mJ
V/ns
W
W
W/ C
o
-7.0
+
30
_
143
-1.75
2.0
-5.0
3.1
20
0.16
- 55 to +150
o
C
300
Thermal Resistance
Symbol
R
θ
JC
R
θ
JA
R
θ
JA
Characteristic
Junction-to-Case
Junction-to-Ambient *
Junction-to-Ambient
Typ.
--
--
--
Max.
6.25
40
62.5
o
Units
C/W
*
When mounted on the minimum pad size recommended (PCB Mount).
Rev. B
©1999 Fairchild Semiconductor Corporation
SFW/I9610
Symbol
BV
DSS
∆BV/∆T
J
V
GS(th)
I
GSS
I
DSS
R
DS(on)
g
fs
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
Q
g
Q
gs
Q
gd
Characteristic
Drain-Source Breakdown Voltage
Breakdown Voltage Temp. Coeff.
Gate Threshold Voltage
Gate-Source Leakage , Forward
Gate-Source Leakage , Reverse
Drain-to-Source Leakage Current
Static Drain-Source
On-State Resistance
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain( “ Miller “ ) Charge
Min. Typ. Max. Units
-200
--
-2.0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
-0.2
--
--
--
--
--
--
1.1
220
45
16
10
20
27
12
9
1.8
4.8
--
--
-4.0
-100
100
-10
-100
3.0
--
285
65
25
30
50
65
35
11
--
--
nC
ns
pF
µA
Ω
Ω
V
o
P-CHANNEL
POWER MOSFET
Electrical Characteristics
(T
C
=25
o
C unless otherwise specified)
Test Condition
V
GS
=0V,I
D
=-250µA
See Fig 7
V
DS
=-5V,I
D
=-250µA
V
GS
=-30V
V
GS
=30V
V
DS
=-200V
V
DS
=-160V,T
C
=125 C
V
GS
=-10V,I
D
=-0.9A
V
DS
=-40V,I
D
=-0.9A
4
O
4
O
o
V/ C I
D
=-250µA
V
nA
V
GS
=0V,V
DS
=-25V,f =1MHz
See Fig 5
V
DD
=-100V,I
D
=-1.75A,
R
G
=18
Ω
See Fig 13
4
5
OO
V
DS
=-160V,V
GS
=-10V,
I
D
=-1.75A
See Fig 6 & Fig 12
4
5
OO
Source-Drain Diode Ratings and Characteristics
Symbol
I
S
I
SM
V
SD
t
rr
Q
rr
Characteristic
Continuous Source Current
Pulsed-Source Current
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
1
O
4
O
Min. Typ. Max. Units
--
--
--
--
--
--
--
--
110
0.42
-1.75
-7.0
-4.0
--
--
A
V
ns
µC
Test Condition
Integral reverse pn-diode
in the MOSFET
T
J
=25 C,I
S
=-1.75A,V
GS
=0V
T
J
=25 C,I
F
=-1.75A
di
F
/dt=100A/µs
4
O
o
o
Notes ;
1
O
Repetitive Rating : Pulse Width Limited by Maximum Junction Temperature
2
O
L=70mH, I
AS
=-1.75A, V
DD
=-50V, R
G
=27Ω
*
, Starting T
J
=25
o
C
3
_
<
<
O
I
SD
_
-1.75A, di/dt
<
250A/µs, V
DD
_
BV
DSS
, Starting T
J
=25
o
C
4
Pulse Test : Pulse Width = 250
µs,
Duty Cycle
<
2%
_
O
5
O
Essentially Independent of Operating Temperature
P-CHANNEL
POWER MOSFET
Fig 1. Output Characteristics
V
GS
- 15 V
- 10 V
- 8.0 V
- 7.0 V
- 6.0 V
- 5.5 V
- 5.0 V
Bottom : - 4.5 V
SFW/I9610
Fig 2. Transfer Characteristics
[A]
-I
D
, Drain Current
10
0
150
o
C
25
o
C
@ Notes :
1. V = 0 V
GS
2. V = -40 V
DS
- 55 C
10
1
10
-1
2
4
6
o
-I
D
, Drain Current
[A]
Top :
10
0
10
-1
@ Notes :
1. 250
µ
s Pulse Test
2. T = 25
o
C
C
0
10
3. 250
µ
s Pulse Test
10
-1
8
10
-V
DS
, Drain-Source Voltage [V]
-V
GS
, Gate-Source Voltage [V]
R
DS(on)
, [ ]
Ω
Drain-Source On-Resistance
10
8
6
V
GS
= -10 V
4
-I
DR
, Reverse Drain Current
[A]
Fig 3. On-Resistance vs. Drain Current
Fig 4. Source-Drain Diode Forward Voltage
10
0
150
o
C
@ Notes :
1. V = 0 V
GS
2. 250
µ
s Pulse Test
2
V
GS
= -20 V
0
0
1
2
3
4
5
6
7
@ Note : T = 25
o
C
J
25
o
C
10
-1
0.5
1.0
1.5
2.0
2.5
3.0
-I
D
, Drain Current [A]
-V
SD
, Source-Drain Voltage [V]
Fig 5. Capacitance vs. Drain-Source Voltage
C
iss
= C
gs
+ C ( C
ds
= shorted )
gd
Fig 6. Gate Charge vs. Gate-Source Voltage
[V]
400
C
iss
300
C
oss
200
C
rss
100
@ Notes :
1. V = 0 V
GS
2. f = 1 MHz
C
oss
= C
ds
+ C
gd
C
rss
= C
gd
[pF]
-V
GS
, Gate-Source Voltage
10
V
DS
= -40 V
V = -100 V
DS
V = -160 V
DS
Capacitance
5
@ Notes : I =-1.75 A
D
0
0
2
4
6
8
10
0
10
0
1
10
-V
DS
, Drain-Source Voltage [V]
Q
G
, Total Gate Charge [nC]
SFW/I9610
-BV
DSS
, (Normalized)
Drain-Source Breakdown Voltage
P-CHANNEL
POWER MOSFET
Fig 8. On-Resistance vs. Temperature
Drain-Source On-Resistance
3.0
Fig 7. Breakdown Voltage vs. Temperature
1.2
R
DS(on)
, (Normalized)
2.5
1.1
2.0
1.0
1.5
1.0
@ Notes :
1. V = -10 V
GS
2. I = -0.9 A
D
0.9
@ Notes :
1. V = 0 V
GS
2. I = -250
µ
A
D
0.5
0.8
-75
-50
-25
0
25
50
75
100
125
150
175
0.0
-75
-50
-25
0
25
50
75
100
125
150
175
T
J
, Junction Temperature [
o
C]
T
J
, Junction Temperature [
o
C]
[A]
Fig 9. Max. Safe Operating Area
Operation in This Area
is Limited by R
DS(on)
10
1
0.1 ms
1 ms
10
0
10 ms
DC
@ Notes :
1. T = 25
o
C
C
2. T = 150
o
C
J
3. Single Pulse
Fig 10. Max. Drain Current vs. Case Temperature
[A]
-I
D
, Drain Current
2.0
-I
D
, Drain Current
1.5
1.0
10
-1
0.5
10
-2
10
0
10
1
10
2
0.0
25
50
75
100
o
125
150
-V
DS
, Drain-Source Voltage [V]
T
c
, Case Temperature [ C]
Fig 11. Thermal Response
Thermal Response
D=0.5
@ Notes :
1. Z
θ
J C
(t)=6.25
o
C/W Max.
2. Duty Factor, D=t
1
/t
2
3. T
J M
-T
C
=P
D M
*Z
θ
J C
(t)
0.05
0.02
0.01
10
- 1
single pulse
0.2
10
0
0.1
P
.
DM
t
1.
t
2.
Z
θ
JC
(t) ,
10
- 5
10
- 4
10
- 3
10
- 2
10
- 1
10
0
10
1
t
1
, Square Wave Pulse Duration
[sec]
P-CHANNEL
POWER MOSFET
Fig 12. Gate Charge Test Circuit & Waveform
SFW/I9610
“ Current Regulator ”
50KΩ
12V
200nF
300nF
Same Type
as DUT
V
GS
Q
g
-10V
V
DS
V
GS
DUT
-3mA
Q
gs
Q
gd
R
1
Current Sampling (I
G
)
Resistor
R
2
Current Sampling (I
D
)
Resistor
Charge
Fig 13. Resistive Switching Test Circuit & Waveforms
R
L
V
out
V
in
R
G
DUT
-10V
V
out
90%
t
on
t
off
t
r
t
d(off)
t
f
V
DD
( 0.5 rated V
DS
)
t
d(on)
V
in
10%
Fig 14. Unclamped Inductive Switching Test Circuit & Waveforms
L
L
V
DS
Vary t
p
to obtain
required peak I
D
BV
DSS
1
2
--------------------
E
AS
= ---- L
L
I
AS
2
BV
DSS
-- V
DD
t
p
I
D
V
DD
Time
V
DS
(t)
R
G
DUT
-10V
t
p
C
V
DD
I
D
(t)
I
AS
BV
DSS
MEMS传感器
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