Maximum Lead Temperature for Soldering Purposes 1/8″ from Case for 10 Seconds
Symbol
R
θJC
R
θJA
T
L
Value
1.2
60
260
Unit
°C/W
°C/W
°C
ELECTRICAL CHARACTERISTICS
(T
C
= 25°C unless otherwise indicated; Electricals apply in both directions)
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Peak Repetitive Blocking Current
(V
D
= Rated V
DRM
, V
RRM
; Gate Open)
T
J
= 25°C
T
J
= 125°C
I
DRM,
I
RRM
—
—
—
—
10
2.0
μA
mA
ON CHARACTERISTICS
Peak On−State Voltage (I
TM
=
"35
A Peak, Pulse Width
v
2 ms,
Duty Cycle
v
2%)
Gate Trigger Current (Continuous dc)
(V
D
= 12 V, R
L
= 100
Ω)
MT2(+), G(+); MT2(−), G(−); MT(+), G(−)
MT2(−), G(+)
Gate Trigger Voltage (Continuous dc)
(V
D
= 12 V, R
L
= 100
Ω)
MT2(+), G(+); MT2(−), G(−); MT(+), G(−)
MT2(−), G(+)
Gate Non−trigger Voltage
(V
D
= 12 V, T
J
= 125°C, R
L
= 100
Ω)
All Quadrants
Holding Current
(V
D
= 12 Vdc, Gate Open, Initiating Current =
"200
mA)
Turn−On Time
(V
D
= Rated V
DRM
, I
TM
= 35 A Peak, I
G
= 200 mA)
V
TM
I
GT
—
—
V
GT
—
—
V
GD
0.2
—
—
1.1
1.3
0.4
10
1.5
2.0
2.5
Volts
—
50
—
mA
μs
20
30
50
75
Volts
—
1.4
1.85
Volts
mA
I
H
t
gt
DYNAMIC CHARACTERISTICS
Critical Rate of Rise of Off-State Voltage
(V
D
= Rated V
DRM
, Exponential Waveform, T
C
= 125°C)
Critical Rate of Rise of Commutation Voltage
(V
D
= Rated V
DRM
, I
TM
= 35 A Peak, Commutating
di/dt = 12.6 A/ms, Gate Unenergized, T
C
= 80°C)
dv/dt
dv/dt(c)
—
—
40
5.0
—
—
V/μs
V/μs
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2
MAC223A6, MAC223A8, MAC223A10
Voltage Current Characteristic of Triacs
(Bidirectional Device)
+ Current
Quadrant 1
MainTerminal 2 +
Symbol
V
DRM
I
DRM
V
RRM
I
RRM
V
TM
I
H
Parameter
Peak Repetitive Forward Off State Voltage
Peak Forward Blocking Current
Peak Repetitive Reverse Off State Voltage
Peak Reverse Blocking Current
Maximum On State Voltage
Holding Current
Quadrant 3
MainTerminal 2
−
I
H
V
TM
I
RRM
at V
RRM
on state
I
H
V
TM
off state
+ Voltage
I
DRM
at V
DRM
Quadrant Definitions for a Triac
MT2 POSITIVE
(Positive Half Cycle)
+
(+) MT2
(+) MT2
Quadrant II
(−) I
GT
GATE
MT1
REF
(+) I
GT
GATE
MT1
REF
Quadrant I
I
GT
−
(−) MT2
(−) MT2
+ I
GT
Quadrant III
(−) I
GT
GATE
MT1
REF
(+) I
GT
GATE
MT1
REF
−
MT2 NEGATIVE
(Negative Half Cycle)
Quadrant IV
All polarities are referenced to MT1.
With in−phase signals (using standard AC lines) quadrants I and III are used.
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3
MAC223A6, MAC223A8, MAC223A10
TC , MAXIMUM ALLOWABLE CASE TEMPERATURE (
°
C)
125
115
105
95
85
75
0
5.0
10
15
20
25
I
T(RMS)
, RMS ON−STATE CURRENT (AMPS)
PD, AVERAGE POWER DISSIPATION (WATTS)
40
30
20
10
0
0
5.0
10
15
20
I
T(RMS)
, RMS ON−STATE CURRENT (AMPS)
25
Figure 1. RMS Current Derating
Figure 2. On−State Power Dissipation
NORMALIZED GATE CURRENT
3.0
2.0
1.0
0.5
0.3
0.2
0.1
−60
−40
−20
100
0
20
40
60
80
T
J
, JUNCTION TEMPERATURE (°C)
120
140
V
D
= 12 V
R
L
= 100
Ω
NORMALIZED GATE VOLTAGE
3.0
2.0
1.0
0.5
0.3
0.2
0.1
−60
−40
−20
0
20
40
60
80 100
T
J
, JUNCTION TEMPERATURE (°C)
120
140
V
D
= 12 V
R
L
= 100
Ω
Figure 3. Typical Gate Trigger Current
i TM, INSTANTANEOUS ON−STATE CURRENT (AMPS)
Figure 4. Typical Gate Trigger Voltage
NORMALIZED HOLD CURRENT
200
100
50
10
5.0
1.0
0.5
0.1
0
1.0
2.0
3.0
4.0
T
J
= 25°C
2.0
1.0
0.5
0.3
0.2
0.1
−60
−40
−20
0
20
40
I
TM
= 200 mA
Gate Open
60
80
100
120
140
T
J
, JUNCTION TEMPERATURE (°C)
V
TM
, INSTANTANEOUS ON−STATE VOLTAGE (VOLTS)
Figure 5. Typical Hold Current
Figure 6. Typical On−State Characteristics
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4
MAC223A6, MAC223A8, MAC223A10
PACKAGE DIMENSIONS
TO−220AB
CASE 221A−07
ISSUE Z
−T−
B
F
T
C
SEATING
PLANE
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
DIM
A
B
C
D
F
G
H
J
K
L
N
Q
R
S
T
U
V
Z
INCHES
MIN
MAX
0.570
0.620
0.380
0.405
0.160
0.190
0.025
0.035
0.142
0.147
0.095
0.105
0.110
0.155
0.014
0.022
0.500
0.562
0.045
0.060
0.190
0.210
0.100
0.120
0.080
0.110
0.045
0.055
0.235
0.255
0.000
0.050
0.045
−−−
−−−
0.080
MILLIMETERS
MIN
MAX
14.48
15.75
9.66
10.28
4.07
4.82
0.64
0.88
3.61
3.73
2.42
2.66
2.80
3.93
0.36
0.55
12.70
14.27
1.15
1.52
4.83
5.33
2.54
3.04
2.04
2.79
1.15
1.39
5.97
6.47
0.00
1.27
1.15
−−−
−−−
2.04
Q
H
Z
L
V
G
4
1 2 3
A
U
K
R
J
D
N
STYLE 4:
PIN 1.
2.
3.
4.
MAIN TERMINAL 1
MAIN TERMINAL 2
GATE
MAIN TERMINAL 2
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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