Doc No.
TA4-EA-06187
Revision.
2
Product Standards
NN30320A
http://www.semicon.panasonic.co.jp/en/
3 A Synchronous DC-DC Step down Regulator
(V
IN
= 4.5 V to 28 V, V
OUT
= 0.75 V to 5.5 V)
FEATURES
High-Speed Response DC-DC Step Down Regulator
Circuit that employs Hysteretic Control System
Two 20 m (Typ) MOSFETs
for High Efficiency at 3 A
Skip (discontinuous) mode for Light Load Efficiency
Maximum Output Current : 3 A
Input Voltage Range : AV
IN
= 4.5 V to 28 V,
PV
IN
= 4.5 V to 28 V
Output Voltage Range : 0.75 V to 5.5 V
Selectable Switching Frequency
: 210 kHz, 430 kHz, 650 kHz
Adjustable Soft Start
Low Operating and Standby Quiescent Current
Power Good Indication for Output Over and
Under Voltage
Built-in Under Voltage Lockout (UVLO),
Thermal Shut Down (TSD),
Over Voltage Detection (OVD),
Under Voltage Detection (UVD),
Over Current Protection (OCP),
Short Circuit Protection (SCP)
24 pin Plastic Quad Flat Non-leaded Package Heat
Slug Down (QFN Type)
(Size : 4 mm
4 mm
0.7 mm, 0.5 mm pitch)
DESCRIPTION
NN30320A is a synchronous DC-DC Step down
Regulator (1-ch) comprising of a Controller IC and two
power MOSFETs and employs the hysteretic control
system.
By this system, when load current changes suddenly,
it responds at high speed and minimizes the changes
of output voltage.
Since it is possible to use capacitors with small
capacitance and it is unnecessary to add external parts
for system phase compensation, this IC realizes
downsizing of set and reducing in the number of
external parts. Output voltage is adjustable by user.
Maximum current is 3 A.
APPLICATIONS
High Current Distributed Power Systems such as
・HDDs
(Hard Disk Drives)
・SSDs
(Solid State Drives)
・PCs
・Game
consoles
・Servers
・Security
Cameras
・Network
TVs
・Home
Appliances
・OA
Equipment etc.
APPLICATION CIRCUIT EXAMPLE
VREG
EFFICIENCY CURVE
PVIN
10
µF
2
0.1
µF
PVIN
EN
100 k
PGOOD
VOUT
AVIN
BST
AVIN
NN30320A
LX
0.1
µF
1
µH
V
OUT
= 1.2 V
10
µF
2
1.5 k
1.5 k
VFB
VREG
1
µF
SS
AGND PGND
22
µF
2
0.1
µF
10 nF
Note : The application circuit is an example. The operation of
the mass production set is not guaranteed. Sufficient
evaluation and verification is required in the design of
the mass production set. The Customer is fully
responsible for the incorporation of the above
illustrated application circuit in the design of the
equipment.
Condition :
V
IN
= 12 V, V
OUT
Setting = 1.05 V, 1.2 V, 1.8 V, 3.3 V, 5.0 V,
Switching Frequency = 650 kHz, FCCM / Skip mode,
L
O
= 1 µH, C
O
= 44 µF (22 µF
2)
Page 1 of 32
Established : 2013-06-20
Revised
: 2015-02-08
Doc No.
TA4-EA-06187
Revision.
2
Product Standards
NN30320A
ORDERING INFORMATION
Order Number
NN30320A-VB
Feature
Maximum Output Current : 3 A
Package
24 pin HQFN
Output Supply
Emboss Taping
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply voltage
Operating free-air temperature
Operating junction temperature
Storage temperature
Symbol
V
IN
T
opr
T
j
T
stg
V
MODE
,V
FSEL
,V
OUT
,V
FB
V
EN
V
PGOOD
Output Voltage Range
V
LX
ESD
HBM
– 0.3 to (V
IN
+ 0.3)
2
V
kV
*1
*4
—
Rating
30
– 40 to + 85
– 40 to + 150
– 55 to + 150
– 0.3 to (V
REG
+ 0.3)
– 0.3 to 6.0
– 0.3 to (V
REG
+ 0.3)
Unit
V
C
C
C
V
V
V
Notes
*1
*2
*2
*2
*1
*3
*1
*1
*3
Input Voltage Range
Notes : This product may sustain permanent damage if subjected to conditions higher than the above stated absolute
maximum rating. This rating is the maximum rating and device operating at this range is not guaranteed as it
is higher than our stated recommended operating range.
When subjected under the absolute maximum rating for a long time, the reliability of the product may be affected.
V
IN
is voltage for AVIN, PVIN. V
IN
= AV
IN
= PV
IN
.
Do not apply external currents and voltages to any pin not specifically mentioned.
*1 : The values under the condition not exceeding the above absolute maximum ratings and
the power dissipation.
*2 : Except for the power dissipation, operating ambient temperature, and storage temperature,
all ratings are for T
a
= 25
C.
*3 : (V
REG
+ 0.3) V must not exceed 6 V.
*4 : (V
IN
+ 0.3) V must not exceed 30 V.
Page 2 of 32
Established : 2013-06-20
Revised
: 2015-02-08
Doc No.
TA4-EA-06187
Revision.
2
Product Standards
NN30320A
POWER DISSIPATION RATING
Package
24 pin Plastic Quad Flat Non-leaded
Package Heat Slug Down (QFN Type)
j-a
59.7
C
/ W
40.4
C
/ W
j-C
8.9
C
/ W
7.1
C
/ W
PD
(Ta = 25
C)
2.094 W
3.094 W
PD
(Ta = 85
C)
1.088 W
1.608 W
Notes
*1
*2
Notes : For the actual usage, please follow the power supply voltage, load and ambient temperature conditions to ensure that there is
enough margin and the thermal design does not exceed the allowable value.
*1:Glass Epoxy Substrate (4 Layers) [50
50
0.8 t (mm)]
*2:Glass Epoxy Substrate (4 Layers) [50
50
1.57 t (mm)]
CAUTION
Although this IC has built-in ESD protection circuit, it may still sustain permanent damage if not handled
properly. Therefore, proper ESD precautions are recommended to avoid electrostatic damage to the MOS
gates.
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply voltage range
Symbol
AV
IN
PV
IN
V
MODE
Input Voltage Range
V
FSEL
V
EN
Output Voltage Range
V
PGOOD
V
LX
Min
4.5
4.5
– 0.3
– 0.3
– 0.3
– 0.3
– 0.3
Typ
12
12
—
—
—
—
—
Max
28
28
V
REG
+ 0.3
V
REG
+ 0.3
5.0
V
REG
+ 0.3
V
IN
+ 0.3
Unit
V
V
V
V
V
V
V
Notes
—
—
*1
*1
—
*1
*2
Notes : Voltage values, unless otherwise specified, are with respect to GND.
GND is voltage for AGND, PGND. AGND = PGND
V
IN
is voltage for AVIN, PVIN. V
IN
= AV
IN
= PV
IN
.
Do not apply external currents or voltages to any pin not specifically mentioned.
*1 : (V
REG
+ 0.3) V must not exceed 6 V.
*2 : (V
IN
+ 0.3) V must not exceed 30 V.
Page 3 of 32
Established : 2013-06-20
Revised
: 2015-02-08
Doc No.
TA4-EA-06187
Revision.
2
Product Standards
NN30320A
ELECTRICAL CHARACTERISTICS
C
O
= 22 µF
2, L
O
= 1 µH, V
OUT
Setting = 1.2 V, V
IN
= AV
IN
= PV
IN
= 12 V,
Switching Frequency = 650 kHz, V
MODE
= V
REG
(FCCM)
T
a
= 25
C
2
C
unless otherwise noted.
Parameter
Current Consumption
V
EN
= 5 V, I
OUT
= 0 A
R
FB1
= 1.5 k
R
FB2
= 1.5 k
V
MODE
= GND
(Skip mode)
V
EN
= 0 V
Symbol
Condition
Limits
Min
Typ
Max
Unit Note
Consumption current at active
I
OPR
—
650
1000
µA
—
Consumption current at standby
Logic Pin Characteristics
EN pin Low level input voltage
EN pin High level input voltage
EN pin leak current
MODE pin Low level input voltage
MODE pin High level input voltage
MODE pin leak current
FSEL pin Low level input voltage
FSEL pin High level input voltage
FSEL pin leak current
VREG Characteristics
Output voltage
Line regulation
I
STB
—
2
4
µA
—
V
ENL
V
ENH
I
leakEN
V
MDL
V
MDH
I
leakMD
V
FSL
V
FSH
I
leakFS
V
FSEL
= 5 V
V
EN
= 5 V
—
—
—
1.5
—
—
—
6.25
—
—
25
—
V
REG
– 0.1
15.0
0.3
5.0
12.5
V
REG
0.3
V
REG
50
0.3
—
25.0
V
V
µA
V
V
µA
V
V
µA
—
—
—
—
—
—
—
*1
—
—
—
V
MODE
= 5 V
—
—
—
V
REG
0.7
—
—
—
—
V
REG
V
REGLIN
I
VREG
= 6 mA
V
REGLIN
= V
REG
(V
IN
= 12 V)
– V
REG
(V
IN
= 6 V)
I
VREG
= 6 mA
V
IN
= 4.5 V
I
VREG
= 6 mA
5.4
—
5.7
—
6.0
200
V
mV
—
—
Drop out voltage
Note :
*1 : Typical design value
V
REGDO
4.11
—
—
V
—
Page 4 of 32
Established : 2013-06-20
Revised
: 2015-02-08
Doc No.
TA4-EA-06187
Revision.
2
Product Standards
NN30320A
ELECTRICAL CHARACTERISTICS (Continued)
C
O
= 22 µF
2, L
O
= 1 µH, V
OUT
Setting = 1.2 V, V
IN
= AV
IN
= PV
IN
= 12 V,
Switching Frequency = 650 kHz, V
MODE
= V
REG
(FCCM)
T
a
= 25
C
2
C
unless otherwise noted.
Parameter
VFB Characteristics
VFB comparator threshold
VFB pin leak current 1
VFB pin leak current 2
Under Voltage Lockout (UVLO)
UVLO detection voltage
UVLO recover voltage
PGOOD Characteristics
PGOOD Threshold 1
(V
FB
ratio for UVD detect)
PGOOD Hysteresis 1
(V
FB
ratio for UVD release)
PGOOD Threshold 2
(V
FB
ratio for OVD detect)
PGOOD Hysteresis 2
(V
FB
ratio for OVD release)
PGOOD ON resistance
V
PGUV
V
PGUV
V
PGOV
V
PGOV
R
PGOOD
V
PGOOD
: High to Low
V
PGOOD
: Low to High
V
PGOOD
: High to Low
V
PGOOD
: Low to High
—
77
3.5
107
3.5
—
85
5.0
115
5.0
10
93
6.5
123
6.5
15
%
%
%
%
—
—
—
—
—
V
UVLODE
V
UVLORE
V
IN
= 5 V to 0 V
V
IN
= 0 V to 5 V
3.5
3.9
3.8
4.2
4.1
4.5
V
V
—
—
V
FBTH
I
leakF1
I
leakF2
V
FB
= 0 V
V
FB
= 6 V
—
0.594
–1
–1
0.600
—
—
0.606
1
1
V
µA
µA
—
—
—
Symbol
Condition
Limits
Min
Typ
Max
Unit Note
Page 5 of 32
Established : 2013-06-20
Revised
: 2015-02-08
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