MN103SJ7/N0/N1/N2/N4/N5/N6 Series
32-bit Single-chip Microcontroller
Overview
The MN103S is a 32-bit microcontroller combining ease of use intended for programs development in the C language with a simple,
high-performance architecture made possible through pursuit of cost performance.
Built around a compact 32-bit CPU with a basic instruction word length of 1 byte, this LSI includes internal memory for instructions
and data, DMA controller, a clock generator, bus controller, interrupt controller, watchdog timer, standard peripheral circuitry such as timers
and serial interfaces, PWM circuit best suited to controlling 3-phase motors and A/D converters for motor position control. The MN103S
Series' high-speed CPU coupled with abundance of peripheral features provides an easy means of developing low-cost, high-performance
and multifunctional system on LSI for motor and power control applications requiring fast response - a feature previously unavailable with
conventional microcontrollers.
Product Summary
This datasheet describes the following model.
Model
MN103SFJ7A
MN103SFN0D
MN103SFN0X
MN103SFN0G
MN103SFN0Y
MN103SFN1D
MN103SFN1X
MN103SFN1G
MN103SFN1Y
MN103SFN2D
MN103SFN2X
MN103SFN2G
MN103SFN2Y
MN103SFN4D
MN103SFN4X
MN103SFN4G
MN103SFN4Y
MN103SFN5D
MN103SFN5X
MN103SFN5G
MN103SFN5Y
MN103SFN6D
MN103SFN6X
MN103SFN6G
MN103SFN6Y
ROM
Size
32 KB
64 KB
128 KB
64 KB
128 KB
64 KB
128 KB
64 KB
128 KB
64 KB
128 KB
64 KB
128 KB
RAM
Size
2 KB
4KB
8 KB
6 KB
8 KB
4 KB
8 KB
6 KB
8 KB
4 KB
8 KB
6 KB
8 KB
4 KB
8 KB
6 KB
8 KB
4 KB
8 KB
6 KB
8 KB
4 KB
8 KB
6 KB
8 KB
TQFP80
12/5
2
3
2
2
TQFP080-P-1212D
TQFP64
12/3
2
3
2
2
TQFP064-P-1010C
QFP44
TQFP48
8/2
1
2
2
1
QFP044-P-1010F
TQFP48-P-0707B
TQFP80
12/5
2
3
2
—
TQFP080-P-1212D
TQFP64
12/3
2
3
2
—
TQFP064-P-1010C
QFP44
TQFP48
8/2
1
2
2
—
QFP044-P-1010F
TQFP48-P-0707B
Pins
TQFP48
Timer
(8bit/
16bit)
8/1
PWM
1
Serial
I/F
2
A/D
2
VGA
—
Package
TQFP48-P-0707B
Publication date: September 2013
Ver. DEM
1
MN103SJ7/N0/N1/N2/N4/N5/N6 Series
Features
CPU core
MN103S core
4 GB of address space (for instructions / data)
LOAD/STORE architecture with 5-stage pipeline
46 basic instructions + 8 extension instructions
6 addressing modes
Instruction set of 1 byte in word length
Extension arithmetic unit incorporated (high-speed multiply instruction, high-speed division instruction etc.)
Machine cycle: 16.7 ns (oscillation frequency: 10 MHz, 6 multiplying)
Operation mode: NORMAL mode, SELLP mode, HALT mode, STOP mode
Oscillation Circuit
External oscillation (crystal/ ceramic)
Clock multiply circuit Oscillation clock can be multiplied by from 3 to 12
Internal memory
ROM: 32 K/64 K/128 K bytes
RAM: 2 K/4 K/6 K/8 K bytes
The ROM/RAM size is different in each product.
Please refer to [
Product Summary]
for details.
DMA Controller
Number of channels: 1 channel
Startup sources:
15 sources (MN103SFN0/N4 series)
20 sources (MN103SFN1/N5 series)
22 sources (MN103SFN2/N6 series)
(External interrupts: Max 12 sources, Serial Interface: Max 9 sources, Software start: 1 source)
Transfer modes:
3 modes (One word transfer, Burst transfer, Intermittent transfer)
*: There is not the function in the MN103SFJ7A.
Interrupts
Non-maskable interrupts
Watchdog timer overflow interrupts
System error interrupts
Fail safe function interrupts
Internal interrupts (Level interrupt)
MN103SFJ7A
: 23 interrupts
MN103SFN0/N4 series: 29 interrupts
MN103SFN1/N5 series: 42 interrupts
MN103SFN2/N6 series: 48 interrupts
<Timer Interrupts>
Timer 0 underflow interrupt
Timer 1 underflow interrupt
Timer 2 underflow interrupt
Timer 3 underflow interrupt
Timer 4 underflow interrupt
Timer 5 underflow interrupt
Timer 6 underflow interrupt
Timer 7 underflow interrupt
Timer 8 underflow interrupt
Timer 9 underflow interrupt
Timer 10 underflow interrupt
Timer 11 underflow interrupt
Timer 16 overflow/underflow interrupt
Timer 16 compare/capture A interrupt
Ver. DEM
2
MN103SJ7/N0/N1/N2/N4/N5/N6 Series
Features (continued)
<Timer Interrupts> (continued)
Timer 16 compare/capture B interrupt
Timer 17 overflow/underflow interrupt
Timer 17 compare/capture A interrupt
Timer 17 compare/capture B interrupt
Timer 18 overflow/underflow interrupt
Timer 18 compare/capture A interrupt
Timer 18 compare/capture B interrupt
Timer 19 overflow/underflow interrupt
Timer 19 compare/capture A interrupt
Timer 19 compare/capture B interrupt
Timer 20 overflow/underflow interrupt
Timer 20 compare/capture A interrupt
Timer 20 compare/capture B interrupt
<Serial Interface>
Serial 0 reception end interrupts
Serial 0 communication/transmission end interrupts
Serial 1 reception end interrupts
Serial 1 communication/transmission end interrupts
Serial 2 reception end interrupts
Serial 2 communication/transmission end interrupts
<PWM>
PWM0 overflow interrupts
PWM0 underflow interrupts
PWM0 synchronous A/D start A
PWM0 synchronous A/D start B
PWM1 overflow interrupts
PWM1 underflow interrupts
PWM1 synchronous A/D start A
PWM1 synchronous A/D start B
<A/D>
A /D 0 conversion end interrupt
A /D 0 conversion end B interrupt
A /D 1 conversion end interrupt
A /D 1 conversion end B interrupt
<DMA>
DMA transfer end interrupt
DMA request after DMA transfer end interrupt
DMA transfer request overflow interrupt
External interrupts:
MN103SFJ7A
MN103SFN0/N4 series
MN103SFN1/N5 series
MN103SFN2/N6 series
:
:
:
:
4 interrupts
8 interrupts
10 interrupts
12 interrupts
External interrupt pins
: From IRQ00 to IRQ11
Interrupt detection condition : Each edge, both edges, high-level and low-level detection
Each interrupt detection condition is able to filtering with the noise filter
Ver. DEM
3
MN103SJ7/N0/N1/N2/N4/N5/N6 Series
Features (continued)
Timer counter
8-bit timer
16-bit timer
8
12
1
2
3
5
sets (MN103SFJ7A, MN103SFN0/N4 series)
sets (MN103SFN1/N5, MN103SFN2/N6 series)
sets (MN103SFJ7A)
sets (MN103SFN0/N4 series)
sets (MN103SFN1/N5 series)
sets (MN103SFN2/N6 series)
Timer 0 (8-bit timer)
Interval timer, Timer pulse output, Event count, Baud rate timer
Count clock source : IOCLK, IOCLK/8, IOCLK/32, IOCLK/128, TM0IO pin input,
Timer 1 underflow, Timer 2 underflow
Timer 1 (8-bit timer)
Interval timer, Timer pulse output, Event count, Baud rate timer, Cascade connection (connected to Timer 0)
Count clock source : IOCLK, IOCLK/8, IOCLK/32, IOCLK/128, TM1IO pin input,
Timer 0 underflow, Timer 2 underflow
Timer 2 (8-bit timer)
Interval timer, Timer pulse output
*1
, Event count
*1
, Baud rate timer, Cascade connection (connected to Timer 1)
Count clock source : IOCLK, IOCLK/8, IOCLK/32, IOCLK/128, TM2IO pin input
*1
,
Timer 0 underflow, Timer 1 underflow
Timer 3 (8-bit timer)
Interval timer, Timer pulse output
*1
, Event count
*1
, Baud rate timer, Cascade connection (connected to Timer 2)
Count clock source : IOCLK, IOCLK/8, IOCLK/32, IOCLK/128, TM3IO pin input
*1
,
Timer 0 underflow, Timer 1 underflow, Timer 2 underflow
Timer 4 (8-bit timer)
Interval timer, Timer pulse output, Event count
Count clock source : IOCLK, IOCLK/8, IOCLK/32, IOCLK/128, TM4IO pin input,
Timer 5 underflow, Timer 6 underflow
Timer 5 (8-bit timer)
Interval timer, Timer pulse output, Event count, Cascade connection (connected to Timer 4)
Count clock source : IOCLK, IOCLK/8, IOCLK/32, IOCLK/128, TM5IO pin input,
Timer 4 underflow, Timer 6 underflow
Timer 6 (8-bit timer)
Interval timer, Timer pulse output, Event count, Cascade connection (connected to Timer 5)
Count clock source : IOCLK, IOCLK/8, IOCLK/32, IOCLK/128, TM6IO pin input,
Timer 4 underflow, Timer 5 underflow
Timer 7 (8-bit timer)
Interval timer, Timer pulse output, Event count, Cascade connection (connected to Timer 6)
Count clock source : IOCLK, IOCLK/8, IOCLK/32, IOCLK/128, TM7IO pin input,
Timer 4 underflow, Timer 5 underflow, Timer 6 underflow
Timer 8 (8-bit Timer )
*2
Interval timer, Timer pulse output
*3
, Event count
*3
Count clock source : IOCLK, IOCLK/8, IOCLK/32, IOCLK/128, TM8IO pin input
*3
,
Timer 9 underflow, Timer 10 underflow
Ver. DEM
4
MN103SJ7/N0/N1/N2/N4/N5/N6 Series
Features (continued)
Timer counter (continued)
Timer 9 (8-bit timer)
*2
Interval timer, Timer pulse output
*3
, Event count
*3
, Cascade connection (Connected to Timer 8)
Count clock source : IOCLK, IOCLK/8, IOCLK/32, IOCLK/128, TM9IO pin input
*3
,
Timer 8 underflow, Timer 10 underflow
Timer 10 (8-bit timer)
*2
Interval timer, Timer pulse output, Event count, Cascade connection (Connected to Timer 9)
Count clock source : IOCLK, IOCLK/8, IOCLK/32, IOCLK/128, TM10IO pin input,
Timer 8 underflow, Timer 9 underflow
Timer 11 (8-bit timer)
*2
Interval timer, Timer pulse output, Event count, Cascade connection (Connected to Timer 10)
Count clock source : IOCLK, IOCLK/8, IOCLK/32, IOCLK/128, TM11IO pin input,
Timer 8 underflow, Timer 9 underflow, Timer 10 underflow
Timer 16 (16-bit timer)
Interval timer, Event count, Up/down count, Timer output, PWM output, Input capture, one-shot output, External trigger start
Start by PWMn overflow interrupt, PMWn underflow interrupt, A/D conversion start trigger generation
Count clock source : IOCLK, IOCLK/8, Timer 6 underflow, Timer 7 underflow, TM16BIO pin input
Timer 17 (16-bit timer)
*2 , *4
Interval timer, Event count, Up/down count, Timer output, PWM output, Input capture, one-shot output, External trigger start
Count clock source : IOCLK, IOCLK/8, IOCLK/64, Timer 11 underflow, TM17BIO pin input
Timer 18 (16-bit timer)
*5
Interval timer, Event count, Up/down count, Timer output, PWM output (output to 6 ports all at once is possible),
Input capture, one-shot output, External trigger start
Count clock source : IOCLK, IOCLK/8, IOCLK/64, Timer 7 underflow, TM18BIO pin input
Timer 19 (16-bit timer)
*2
Interval timer, Event count, Up/down count, Timer output, PWM output, Input capture, one-shot output, External trigger start
Start by PWMn overflow interrupt, PWMn underflow interrupt, A/D conversion start trigger generation
Count clock source : IOCLK, IOCLK/8, Timer 10 underflow, Timer 11 underflow, TM19BIO pin input
Timer 20 (16-bit timer)
*2 , *4
Interval timer, Event count, Up/down count, Timer output, PWM output, Input capture, one-shot output, External trigger start,
Count clock source : IOCLK, IOCLK/8, Timer 6 underflow, Timer 7 underflow, TM20BIO pin input
Note) *1: The function using the TMnIO pin (n = 2, 3) cannot be used by the MN103SFN0/N4 series.
*2: There is not the function in the MN103SFN0/N4 series.
*3: The function using the TMnIO pin (n = 8, 9) cannot be used by the MN103SFN1/N5 series.
*4: There is not the function in the MN103SFN1/N5 series.
*5: There is not the function in the MN103SJ7A.
Ver. DEM
5
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
