MN101EFC3/D3 Series
8-bit Single-chip Microcontroller
PubNo. 216C3-014E
1.1 Overview
1.1.1
Overview
The MN101E series of 8-bit single-chip microcomputers (the memory expansion version of MN101C
series) incorporate multiple types of peripheral functions. This chip series is well suited for in-vehicle
body control, in-vehicle AV, camera, VCR, MD, TV, CD, LD, printer, telephone, home automation,
pager, air conditioner, PPC, fax machine, music instrument and other applications.
This LSI brings to embedded microcomputer applications flexible, optimized hardware configurations
and a simple efficient instruction set.
MN101EFC3D has an internal 76 KB of ROM and 6 KB of RAM. MN101EFC3Y has an internal 76 KB
of ROM and 10 KB of RAM. MN101EFC3G has an internal 128 KB of ROM and 6 KB of RAM.
MN101EFC3Z has an internal 128 KB of ROM and 10 KB of RAM. MN101EFD3D has an internal 76
KB of ROM and 10 KB of RAM. MN101EFD3G has an internal 128 KB of ROM and 10 KB of RAM.
Peripheral functions include 5 external interrupts, 34 internal interrupts including NMI, 12 timer
counters, 4 types of serial interfaces, CAN controller (on MN101EFD3D/G) based on CAN 2.0B, A/D
converter, LCD driver, 2 types of watchdog timer, and data automatic function. The system configura-
tion is suitable for in-vehicle body control microcontroller such as in-vehicle body control, heater control,
relay BOX, or various motor controls.
With 5 oscillation systems (high-speed (internal frequency: 20 MHz), high-speed (crystal/ceramic fre-
quency: max. 10 MHz) / low-speed (internal frequency: 30 kHz), low-speed (crystal/ceramic frequency:
32.768 kHz) and PLL: frequency multiplier of high frequency) contained on the chip, the system clock
can be switched to high-speed frequency input (NORMAL mode), PLL input (PLL mode), or to low-
speed frequency input (SLOW mode). The system clock is generated by dividing the oscillation clock or
PLL clock. The best operation clock for the system can be selected by switching its frequency ratio by
programming. High speed mode has the normal mode which is based on the clock dividing fpll, (fpll is
generated by original oscillation and PLL), by 2 (fpll/2), and the double speed mode which is based on
the clock not dividing fpll.
A machine cycle (minimum instruction execution time) in the normal mode is 200 ns when the original
oscillation fosc is 10 MHz (PLL is not used). A machine cycle in the double speed mode, in which the
CPU operates on the same clock as the external clock, is 100 ns when fosc is 10 MHz. A machine cycle
in the PLL mode and in the double speed mode when the internal oscillation frc is 20 MHz (PLL is not
used) is 50 ns (maximum).
Publication date: November 2015
1
MN101EFC3/D3 Series
8-bit Single-chip Microcontroller
PubNo. 216C3-014E
1.1.2
Product Summary
This manual describes the following model.
Table:1.1.1 Product Summary
Table remarks
Model
MN101EFC3D
MN101EFC3Y
MN101EFC3G
MN101EFC3Z
MN101EFD3D
MN101EFD3G
ROM Size
76 KB
76 KB
128 KB
128 KB
76 KB
128 KB
RAM Size
6 KB
10 KB
6 KB
10 KB
10 KB
10 KB
:
With function -: Without function
Classification
Flash EEPROM version
Flash EEPROM version
Flash EEPROM version
Flash EEPROM version
Flash EEPROM version
Flash EEPROM version
TQFP064-P-1010D
LQFP064-P-1414
Package
CAN Controller
-
-
-
-
Only flash EEPROM version, DMOD pin contains an internal pull-up resistor.
When using ICE version, connect pull-up resistor to DMOD on the target board.
..
Publication date: November 2015
2
MN101EFC3/D3 Series
8-bit Single-chip Microcontroller
PubNo. 216C3-014E
1.2 Hardware Functions
Feature
- ROM capacity:76 KB to 128 KB
- RAM capacity: 6 KB to 10 KB
TQFP064-P-1010D (10 mm
10 mm / 0.5 mm pitch/ Halogen free *)
LQFP064-P-1414 (14 mm
14 mm / 0.8 mm pitch)
* Panasonic’s “halogen free” semiconductor products refer to the products made of molding resin and
interposer which conform to the following standards.
- Bromine: 900 ppm (Maximum Concentration Value)
- Chlorine: 900 ppm (Maximum Concentration Value)
- Bromine + Chlorine: 1500 ppm (Maximum Concentration Value)
The above-mentioned standards are based on the numerical value described in IEC61249-2-21.
Antimony and its compounds are not added intentionally.
- Package:
- Machine Cycle:
High-speed mode
0.05
s/20
MHz (2.7 V to 5.5 V)
0.125
s/8
MHz (1.8 V to 5.5 V)
Low-speed mode
62.5
s/32
kHz (1.8 V to 5.5 V)
- Clock Gear Circuit:
Internal system clock speed is changeable by selecting division ratio of oscillation clock.
(Divided by 1, 2, 4, 16, 32, 64, 128)
- Oscillation Circuit: 4 types
High-speed (Internal oscillation: frc), High-speed (crystal/ceramic: fosc),
Low-speed (Internal oscillation: frcs), Low-speed (crystal/ceramic: fx)
High-speed internal oscillation 20 MHz / 16 MHz (selectable)
Low-speed internal oscillation 30 kHz
- Clock Multiplication Circuit:
PLL circuit output clock (fpll) fosc multiplied by 2, 3, 4, 5, 6, 8, 10,
1/2xfrc multiplied by 4, 5 enabled
* When clock multiplication circuit is not used, fpll = fosc or fpll = frc
* Selectable from high-speed clock for peripheral functions (fpll-div) fpll, fpll divided by 2, 4, 8, 16
Publication date: November 2015
3
MN101EFC3/D3 Series
8-bit Single-chip Microcontroller
PubNo. 216C3-014E
- Operation Mode
NORMAL mode (high-speed mode)
PLL mode
SLOW mode (low-speed mode)
HALT mode
STOP mode
and operation clock switching
- Operating Voltage: 1.8 V to 5.5 V
- Operation ambient temperature: -40
C
to +85
C
(Product guaranteed 105
C
is available)
- interrupt:
35 sets
<Overrun interrupt>
- Non-maskable interrupt (NMI)
<Timer interrupt>
- Timer 0 interrupt
- Timer 1 interrupt
- Timer 2 interrupt
- Timer 3 interrupt
- Timer 4 interrupt
- Timer 6 interrupt
- Time-base interrupt
- Timer 7 interrupt
- Timer 7 compare register 2 match interrupt
- Timer 8 interrupt
- Timer 8 compare register 2 match interrupt
- PWM overflow interrupt
- PWM under flow interrupt
- Timer 9 compare register 2 match interrupt
- 24H timer interrupt
- Alarm match interrupt
<Serial interrupt>
- CAN interrupt
- LIN interrupt
- Serial 0 interrupt
- Serial 0 UART reception interrupt
- Serial 1 interrupt
- Serial 1 UART reception interrupt
- Serial 2 interrupt
- Serial 2 UART reception interrupt
- Serial 4 interrupt
- Serial 4 stop condition interrupt
<A/D interrupt>
Publication date: November 2015
4
MN101EFC3/D3 Series
8-bit Single-chip Microcontroller
PubNo. 216C3-014E
- A/D conversion interrupt
<Data automatic transfer interrupt>
- ATC1 interrupt
<Low voltage detection interrupt>
- Low voltage detection interrupt
<External interrupt>
- IRQ0 : Edge selection, noise filter connectable
- IRQ1 : Edge selection, noise filter connectable
- IRQ2 : Edge selection, noise filter connectable, both edge interrupt
- IRQ3 : Edge selection, noise filter connectable, both edge interrupt
- IRQ4 : Edge selection, noise filter connectable, both edge interrupt, key scan interrupt
- Timer Counter x 12 sets
- General-purpose 8-bit timer x 5 sets
- General-purpose 16-bit timer x 2 sets
- Motor control 16-bit timer x 1 set
- 8-bit free-run timer x 1 set
- Time-base timer x 1 set
- Baud rate timer x 1 set
- 24H timer x 1 set
Timer 0 (General-purpose 8-bit timer)
- Square wave output (Timer pulse output), added pulse (2bit) type PWM output can be output to
large current pin TM0IOB, event count, simple pulse width measurement
- Clock source
fpll-div, fpll-div/4, fpll-div/16, fpll-div/32, fpll-div/64, fpll-div/128,
fs/2, fs/4, fs/8, fslow, external clock, timer A output
- Real-time control
Timer (PWM) output is controlled among the three values: “Fixed to High”, “Fixed to Low”, or
“Hi-Z” at falling edge of external interrupt 0 (IRQ0)
Timer 1 (General-purpose 8-bit timer)
- Square wave output (Timer pulse output), event count
16-bit cascade connection (connected with timer 0), timer synchronous output
- Clock source
fpll-div, fpll-div/4, fpll-div/16, fpll-div/32, fpll-div/64, fpll-div/128,
fs/2, fs/4, fs/8, fslow, external clock, timer A output
Timer 2 (General-purpose 8-bit timer)
- Square wave output (Timer pulse output), added pulse (2bit) type PWM output can be output to
large current pin TM2IOB, event count, simple pulse width measurement,
24-bit cascade connection (connected with timer 0, 1), timer synchronous output
Publication date: November 2015
5
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