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MN101E30N

产品描述8-bit Single-chip Microcontroller
产品类别嵌入式处理器和控制器    微控制器和处理器   
文件大小565KB,共49页
制造商Panasonic(松下)
官网地址http://www.panasonic.co.jp/semicon/e-index.html
标准
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MN101E30N概述

8-bit Single-chip Microcontroller

MN101E30N规格参数

参数名称属性值
是否无铅不含铅
是否Rohs认证符合
厂商名称Panasonic(松下)
零件包装代码QFP
包装说明QFP-100
针数100
Reach Compliance Codecompli
具有ADCYES
地址总线宽度20
位大小8
最大时钟频率20 MHz
DAC 通道YES
DMA 通道YES
外部数据总线宽度8
JESD-30 代码S-PQFP-G100
长度18 mm
I/O 线路数量85
端子数量100
PWM 通道YES
封装主体材料PLASTIC/EPOXY
封装代码QFP
封装等效代码QFP100,.9SQ
封装形状SQUARE
封装形式FLATPACK
峰值回流温度(摄氏度)NOT SPECIFIED
电源2.5/5 V
认证状态Not Qualified
RAM(字节)8192
ROM(单词)520192
ROM可编程性MROM
座面最大高度2.85 mm
速度20 MHz
最大供电电压5.5 V
最小供电电压2.2 V
标称供电电压2.5 V
表面贴装YES
技术CMOS
端子形式GULL WING
端子节距0.65 mm
端子位置QUAD
处于峰值回流温度下的最长时间NOT SPECIFIED
宽度18 mm
uPs/uCs/外围集成电路类型MICROCONTROLLER

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MN101E30N/E30R/EF30R
8-bit Single-chip Microcontroller
PubNo. 2163001-019E
1.1 Overview
1.1.1
Overview
The MN101E series of 8-bit single-chip microcomputers (the memory expansion version of MN101C
series) incorporate multiple types of peripheral functions. This chip series is well suited for camera,
VCR, MD, TV, CD, LD, printer, telephone, home automation, pager, air conditioner, PPC, fax machine,
music instrument and other applications.
This LSI brings to embedded microcomputer applications flexible, optimized hardware configurations
and a simple efficient instruction set. The MN101E30 series have an internal 928 KB (maximum) of
ROM and 8 KB (maximum) of RAM. Peripheral functions include 6 external interrupts, 30 internal inter-
rupts including NMI, 9 timer counters, 6 sets of serial interfaces, A/D converter, D/A converter, LCD
driver, watchdog timer, 2 sets of automatic data transfer, synchronous output function and buzzer out-
put. The configuration of this microcomputer is well suited for application as a system controller in cam-
era, timer selector for VCR, CD player, or minicomponent, and also suited for audio reproduction with a
high-precision D/A converter.
With three oscillation system (high frequency: max. 20 MHz / low frequency: 32.768 kHz and PLL: fre-
quency multiplier of high frequency) contained on the chip, the system clock can be switched to high
frequency input (high speed mode), PLL input (PLL mode), or to low frequency input (low speed mode).
The system clock is generated by dividing the oscillation clock. The best operation clock for the system
can be selected by switching its frequency by software. High speed mode has the normal mode based
on fpll/2 which is half clock generated from an original oscillation and PLL, and the double speed mode
based on fpll which is clock generated from an original oscillation without dividing.
A machine cycle (min. instructions execution) in the normal mode is 100 ns when fosc is 20 MHz (at the
time that PLL is not used). A machine cycle in the double speed mode is 50 ns when fosc is 20 MHz. A
machine cycle in the PLL mode is 50 ns (maximum).The package is 100-pin QFP, LQFP.
Publication date: October 2015
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