UNISONIC TECHNOLOGIES CO., LTD
UC3873B
LOW COST POWER-SAVING
MODE PWM CONTROLLER
FOR FLYBACK CONVERTERS
DESCRIPTION
6
5
4
LINEAR INTEGRATED CIRCUIT
2
The
UC3873B
is a high performance current mode PWM
1
controller ideally suited for low standby power. Low V
DD
startup
SOT-26
current make the power reliable on startup design and a large
value resistor could be used in the startup circuit to minimize the
standby power. At no load condition, the IC operates in
power-saving mode for lower standby power, decreasing frequency
for Higher conversion efficiency at light load condition.
The
UC3873B
contains protection with automatic recovery
including OLP (over load protection), programming OTP (over
temperature protection), OVP (over voltage protection), UVLO (V
DD
over voltage clamp and under voltage
lockout).To protect the power MOSFET, Gate-drive output is fixed up to 16V max. The
UC3873B
contains protection
OCP (cycle-by-cycle current limiting).
The internal slope compensation improves system stability at high PWM duty cycle output. Leading-edge
blanking on current sense input removes the signal glitch, which offering minimal external component count in the
design. Excellent EMI performance is achieved with UTC proprietary frequency hopping technique
(ZL201020615247.1) together with soft driver control. Audio noise is eliminated due to switch frequency more than
20kHz during operation.
The
UC3873B
has such applications as: battery charger, power adaptor, set-top box power supplies, ink jet
printers, open-frame SMPS.
3
FEATURES
* Programming OTP for higher security
* Fixed switch frequency 65kHz
* Gate output voltage clamped at 15V
* Low start-up current
* Cycle-by-cycle Current Limiting
* Under voltage lockout (UVLO)
* Few external components required
* UTC proprietary frequency hopping technology for Improved EMI
performance.
* Power-saving mode for high light-load and standby efficiency
* Soft Start
* Dynamic peak current limiting for constant output power
* Built-in synchronized slope compensation
* OLP,OVP and V
DD
clamp for higher security
* -500/+500mA gate driver
ORDERING INFORMATION
Ordering Number
UC3873BG-AG6-R
UC3873BG-AG6-R
(1)Packing Type
(2)Package Type
(3)Green Package
(1) R: Tape Reel
(2) AG6: SOT-26
(3) G: Halogen Free and Lead Freee
Package
SOT-26
Packing
Tape Reel
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Copyright © 2015 Unisonic Technologies Co., Ltd
1 of 9
QW-R103-093.A
UC3873B
MARKING
LINEAR INTEGRATED CIRCUIT
PIN CONFIGURATION
PIN DESCRIPTION
PIN NO.
1
2
3
4
5
6
PIN NAME
GND
FB
RT
SENSE
V
DD
GATE
PIN TYPE
DESCRIPTION
P
Ground.
Feedback input pin. The PWM duty cycle is determined by voltage level
I
into this pin and SENSE pin input.
I
Connected through a NTC resistor to GND for OTP.
Current sense input pin. Connected to MOSFET current sensing resistor
I
node.
P
Power supply.
O
The totem-pole output driver for driving the power MOSFET.
BLOCK DIAGRAM
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QW-R103-093.A
UC3873B
PARAMETER
LINEAR INTEGRATED CIRCUIT
ABSOLUTE MAXIMUM RATINGS
(T
A
=25°C, V
DD
=15V, unless otherwise specified)
SYMBOL
RATINGS
UNIT
Supply Voltage
V
DD
30
V
Input Voltage to FB Pin
V
FB
-0.3 ~ 7
V
Input Voltage to CS Pin
V
SENSE
-0.3 ~ 7
V
Junction Temperature
T
J
+150
C
Operating Temperature
T
OPR
-40 ~ +125
°C
Storage Temperature
T
STG
-50 ~ +150
C
Note: Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.
OPERATING RANGE
PARAMETER
SYMBOL
V
DD
RATINGS
10 ~ 24
UNIT
V
Supply Voltage
ELECTRICAL CHARACTERISTICS
(T
A
=25°C, V
DD
=15V，unless otherwise specified)
TEST CONDITIONS
V
DD
= V
DD(ON)
-0.5V
V
FB
=3.5V
I
VCC
=20mA
MIN
TYP
2.5
0.8
33
13
7
5.4
3
1.8
2.9
1.5
65
22
78
MAX
20
1.8
35
14
8
UNIT
μA
mA
V
V
V
V
V/V
V
V
V
KHz
KHz
%
%
%
%
V
V
mS
mS
V
V
ns
V
V
ns
ns
uA
V
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QW-R103-093.A
PARAMETER
SYMBOL
SUPPLY SECTION
Start Up Current
I
STR
IC Operating current
I
OP
VCC Zener Clamp Voltage
V
CC(clamp)
UNDER-VOLTAGE LOCKOUT SECTION
Start Threshold Voltage
V
THD(ON)
Min. Operating Voltage
V
DD(MIN)
CONTROL SECTION
V
FB
Open Loop Voltage Level
V
FB-OPEN
PWM Input Gain
A
VCS
Burst-Mode Out FB Voltage
V
FB(OUT)
Reduce-Frequency end FB Voltage
V
FB(END)
Burst-Mode Enter FB Voltage
V
FB(IN)
Normal
Switch Frequency
F
SW
Power-Saving
Duty Cycle
D
MAX
Frequency Hopping
F
J(SW)
Frequency VDD Stability
F
DV
Frequency Temperature Stability
F
DT
PROTECTION SECTION
V
CC
Over Voltage Protection Threshold
V
OVP
FB PIN Over Load Protection Threshold
V
OLP
Over Load Protection Delay-Time
T
Delay
Soft start time
T
SS
CURRENT LIMITING SECTION
Peak Current Flat Threshold Voltage
V
CS-F
Peak Current Valley Threshold Voltage
V
CS-V
Lead Edge Blanking Time
T
LEB
DRIVER OUTPUT SECTION
Output Voltage Low State
V
OL
Output Voltage High State
V
OH
Output Voltage Rise Time
t
R
Output Voltage Fall Time
t
F
RT SECTION
Output current of RT pin
I
RT
Threshold voltage for OTP
V
TH_OTP
31
12
6
∆V
FB
/∆V
CS
V
SENSE
=0
V
SENSE
=0
V
SENSE
=0
V
FB
=3.5V
Before enter burst mode
V
FB
=3.5V, V
SENSE
=0
V
DD
=12V~20V
T=-20~100°C
V
FB
=4.0V
60
70
-3
1.5
25
80
27
4.2
88
2.5
0.95
0.65
350
+3
5
5
29
96
V
FB
=4.0V, Duty≥60%
V
FB
=4.0V, Duty=0%
0.85
0.55
1.05
0.75
V
DD
=15V,I
O
=-20mA
V
DD
=12V,I
O
= 20mA
C
L
=1.0nF
C
L
=1.0nF
0.8
11
170
60
100
1.00
105
1.05
110
1.10
UNISONIC TECHNOLOGIES CO., LTD
www.unisonic.com.tw
UC3873B
OPERATION DESCRIPTION
LINEAR INTEGRATED CIRCUIT
The
UC3873B
devices integrate many useful designs into one controller for low-power switch-mode power
supplies. The following descriptions highlight some of the features of the
UC3873
series.
Start-up Current
The start-up current is only 2.5μA. Low start-up current allows a start-up resistor with a high resistance and a
low-wattage to supply the start-up power for the controller. For AC/DC adaptor with universal input range design, a
2.5~3MΩ, 1/8W startup resistor could be used together with a V
DD
capacitor to provide a fast startup and low power
dissipation solution.
Power-Saving Mode Operation
The proprietary Power-Saving Mode function provides linearly decreasing the switching frequency under
light-load conditions for higher efficiency. The feedback voltage, which is sampled from the voltage feedback loop, is
taken as the reference. Once the feedback voltage dropped below the threshold voltage, the switching frequency
starts to decrease. This Power-Saving Mode function dramatically reduces power consumption under light-load
conditions. The 22KHz minimum frequency control also eliminates the audio noise at any loading conditions.
At zero load condition, the magnitude of power loss is in proportion to the number of switching events within a
fixed period of time. Reducing switching events leads to the reduction on the power loss and thus conserves the
energy. The
UC3873B
enter burst mode at standby condition to minimize the switching loss and reduces the
standby power consumption. Power supplies using the
UC3873B
can easily meet even the strictest regulations
regarding standby power consumption.
Switch Frequency Set
The maximum switch frequency is fixed to 65KHz. Switch frequency is modulated by output power P
OUT
during IC
operating. At no load or light load condition, most of the power dissipation in a switching mode power supply is from
switching loss on the MOSFET transistor, the core loss of the transformer and the loss on the snubber circuit. The
magnitude of power loss is in proportion to the number of switching events within a fixed period of time. So lower
switch frequency at lower load, which more and more improve IC’s efficiency at light load. At from no load to light
load condition, The IC will operate at from Burst mode to Reducing Frequency Mode. The relation curve between f
SW
and P
OUT
/P
OUT (MAX)
as followed Fig.1.
Fig.1 The relation curve between f
SW
and relative output power P
OUT
/ P
OUT (MAX)
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4 of 9
QW-R103-093.A
UC3873B
OPERATION DESCRIPTION (Cont.)
LINEAR INTEGRATED CIRCUIT
Frequency Hopping For EMI Improvement
The Frequency hopping is implemented in the IC; there are two oscillators built-in the IC. The first oscillator is to
set the normal switching frequency; the switching frequency is modulated with a period signal generated by the 2nd
oscillator. The relation between the first oscillator and the 2nd oscillator as followed Fig.2. So the tone energy is
evenly spread out, the spread spectrum minimizes the conduction band EMI and therefore eases the system design
in meeting stringent EMI requirement.
Fig.2 Frequency Hopping
Built-in Slope Compensation
Built-in slope compensation circuit greatly improves the close loop stability at CCM and prevents the
sub-harmonic oscillation.
Leading-Edge Blanking
Each time the power MOSFET is switched on, a turn-on spike will inevitably occur at the sense-resistor. To avoid
premature termination of the switching pulse, a 400ns leading-edge blanking time is built in. Conventional RC
filtering can therefore be omitted. During this blanking period, the current-limit comparator is disabled and it cannot
switch off the gate driver.
Constant Output Power Limit
When the SENSE voltage, across the sense resistor R
S
, reaches the threshold voltage, around 0.8V, the output
GATE drive will be turned off after a small propagation delay t
D
. This propagation delay will introduce an additional
current proportional to t
D
×V
IN
/Lp. Since the propagation delay is nearly constant regardless of the input line voltage
V
IN
. Higher input line voltage will result in a larger additional current and hence the output power limit is also higher
than that under low input line voltage. To compensate this variation for wide AC input range, the threshold voltage is
adjusted by the V
IN
current. Since V
IN
pin is connected to the rectified input line voltage through a resistor R
VIN
, a
higher line voltage will generate higher V
IN
current into the V
IN
pin. The threshold voltage is decreased if the V
IN
current is increased. Smaller threshold voltage, forces the output GATE drive to terminate earlier, thus reduce the
total PWM turn-on time and make the output power equal to that of low line input. This proprietary internal
compensation ensures a constant output power limit for wide AC input voltage from 90VAC to 264VAC.
Under Voltage Lockout (UVLO)
The turn-on and turn-off thresholds of the
UC3873B
are fixed internally at V
THD(ON)
/V
DD(MIN)
During start-up, the
hold-up capacitor must be charged to V
THD(ON)
through the start-up resistor, so that the
UC3873B
will be enabled.
The hold-up capacitor will continue to supply V
DD
until power can be delivered from the auxiliary winding of the main
transformer. V
DD
must not drop below V
DD(MIN)
during this start-up process. This UVLO hysteresis window ensures
that hold-up capacitor will be adequate to supply V
DD
during start-up.
Gate Output
The
UC3873B
output stage is a fast totem pole gate driver. Cross conduction has been avoided to minimize heat
dissipation, increase efficiency, and enhance reliability. A good tradeoff is achieved through dead time control. The
low idle loss and good EMI system design is easier to achieve with this dedicated control scheme. An internal 15V
clamp is added for MOSFET gate protection at higher than expected V
DD
input.
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5 of 9
QW-R103-093.A
Microchip MCU
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