Si3035
3 .3 V F C C / J AT E D
I R E C T
A
C C E S S
A
R R A N G E M E N T
Features
Complete DAA includes the following:
!
!
!
!
!
!
3.3 V to 5 V Digital/Analog
Power Supplies
JATE Filter Option
86 dB Dynamic Range TX/RX
Paths
Daisy-Chaining for Up to Eight
Devices
Integrated Ring Detector
3000 V Isolation
!
!
!
!
!
!
!
!
!
Support for Caller ID
Low Profile SOIC Packages
Direct Interface to DSPs
Integrated Modem Codec
Compliant with FCC Part 68
Low-Power Standby Mode
Proprietary ISOcap™ Technology
Pin Compatible with Si3034, Si3032
Optional IIR Digital Filter
Ordering Information
See page 50.
Pin Assignments
Applications
!
!
Si3021 (SOIC)
!
!
V.90 Modems
Voice Mail Systems
Fax Machines
Set Top Boxes
MCLK
FSYNC
SCLK
V
D
SDO
SDI
FC/RGDT
RESET
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
OFHK
RGDT/FSD
M0
V
A
GND
C1A
M1
AOUT
Description
The Si3035 is an integrated direct access arrangement (DAA) chipset that
provides a digital, low-cost, solid-state interface to a telephone line.
Available in two 16-pin small outline packages, it eliminates the need for an
analog front end (AFE), an isolation transformer, relays, opto-isolators, and
a 2- to 4-wire hybrid. The Si3035 dramatically reduces the number of
discrete components and cost required to achieve compliance with FCC
Part 68. The Si3035 interfaces directly to standard modem DSPs and
supports all FCC and JATE out-of-band noise requirements. International
support is provided by the pin compatible Si3034.
Si3021 (TSSOP)
SDO
SDI
FC/RGDT
RESET
AOUT
M1
C1A
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
D
SCLK
FSYNC
MCLK
OFHK
RGDT/FSD
M0
V
A
Functional Block Diagram
Si3021
Si3012
Si3012 (SOIC or TSSOP)
MCLK
SCLK
FSYNC
SDI
SDO
FC/RG T
Isolation
Interface
Isolation
Interface
DC
Termination
VREG 2
VREG
DCT
REXT
IG ND
RNG 1
RNG 2
O ff-Hook
QB
QE
Digital
Interface
Hybrid
O ut
In
TX
RX
HYBD
TSTA
TSTB
IGND
C1B
RNG1
RNG2
QB
QE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
TX
NC
RX
REXT
DCT
HYBD
VREG2
VREG
RG DT/FSD
O FHK
MO DE
RESET
AO UT
Control
Interface
Ring Detect
US Patent # 5,870,046
US Patent # 6,061,009
Other Patents Pending
Si3035-DS12
Rev. 1.2 12/00
Copyright © 2000 by Silicon Laboratories
Si3035
T
A B L E O F
C
O N T E N T S
Section
Page
4
15
16
17
18
18
18
18
19
19
19
20
24
24
25
25
25
26
26
32
32
32
33
34
45
46
48
50
51
52
54
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Isolation Barrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Off-Hook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ring Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Improved JATE Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Generation Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Hook Line Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loop Current Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiple Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Filter Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
In-Circuit Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Exception Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Appendix—UL1950 3rd Edition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Descriptions: Si3021 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Descriptions: Si3012 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOIC Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TSSOP Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rev. 1.2
3
S i3 03 5
Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
1
Ambient Temperature
Si3021 Supply Voltage, Analog
Si3021 Supply Voltage, Digital
3
Notes:
Symbol
T
A
V
A
V
D
Test Condition
K-Grade
Min
2
0
4.75
3.0
Typ
25
5.0
3.3/5.0
Max
2
70
5.25
5.25
Unit
°C
V
V
1.
The Si3035 specifications are guaranteed when the typical application circuit (including component
tolerances) and any Si3021 and any Si3012 are used. See Figure 16 on page 15 for typical application
circuit.
2.
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated.
3.
The digital supply, V
D
, can operate from either 3.3 V or 5.0 V. The Si3021 supports interface to 3.3 V logic when
operating from 3.3 V. The 3.3 V operation applies to both the serial port and the digital signals
RGDT, OFHK, RESET, M0, and M1.
Table 2. Loop Characteristics
(V
A
= Charge Pump, V
D
= +3.3 V ± 0.3 V, T
A
= 0 to 70°C for K-Grade, Refer to Figure 1)
Parameter
DC Termination Voltage
DC Termination Voltage
DC Ring Current (
with caller ID)
DC Ring Current
(w/o caller ID)
AC Termination Impedance
Operating Loop Current
Loop Current Sense Bits
Ring Voltage Detect
Ring Frequency
On-Hook Leakage Current
Ringer Equivalence Num. (
with caller ID)
Ringer Equivalence Num.
(w/o caller ID)
Symbol
V
TR
V
TR
I
RDC
I
RDC
Z
ACT
I
LP
LCS
V
RD
F
R
I
LK
REN
REN
Test Condition
I
L
= 20 mA
I
L
= 105 mA
Min
—
12
—
—
—
20
Typ
—
—
—
—
600
—
155
18
—
—
1.0
0.2
Max
7.7
—
1
20
—
120
—
26
68
1
1.67
—
Unit
V
V
mA
µA
Ω
mA
mA
V
RMS
Hz
µA
—
—
LCS = Fh
180
13
15
V
BAT
= –48 V
—
—
—
TIP
+
600
Ω
Si3012 V
TR
10
µ
F
–
I
L
RING
Figure 1. Test Circuit for Loop Characteristics
4
Rev. 1.2
Si3035
Table 3. DC Characteristics, V
D
= +5 V
(V
A
= +5 V ±5%, V
D
= +5 V ±5%, T
A
= 0 to 70°C for K-Grade)
Parameter
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Power Supply Current, Analog
Power Supply Current, Digital
1
Total Supply Current, Sleep Mode
1
Total Supply Current, Deep Sleep
1,2
Symbol
V
IH
V
IL
V
OH
V
OL
I
L
I
A
I
D
I
A
+ I
D
I
A
+ I
D
Test Condition
Min
3.5
—
Typ
—
—
—
—
—
0.3
14
1.3
0.04
Max
—
0.8
—
0.4
10
1
18
2.5
0.5
Unit
V
V
V
V
µA
mA
mA
mA
mA
I
O
= –2 mA
I
O
= 2 mA
3.5
—
–10
V
A
pin
V
D
pin
PDN = 1, PDL = 0
PDN = 1, PDL = 1
—
—
—
—
Notes:
1.
All inputs at 0.4 or V
D
– 0.4 (CMOS levels). All inputs held static except clock and all outputs unloaded
(Static I
OUT
= 0 mA).
2.
RGDT is not functional in this state.
Table 4. DC Characteristics, V
D
= +3.3 V
(V
A
= Charge Pump, V
D
= +3.3 V ± 0.3 V, T
A
= 0 to 70°C for K-Grade)
Parameter
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Power Supply Current, Analog
1,2
Power Supply Current, Digital
3
Total Supply Current, Sleep Mode
3
Total Supply Current, Deep Sleep
3,4
Power Supply Voltage, Analog
1,5
Symbol
V
IH
V
IL
V
OH
V
OL
I
L
I
A
I
D
I
A
+ I
D
I
A
+ I
D
V
A
Test Condition
Min
2.0
—
Typ
—
—
—
—
—
0.3
9
1.2
0.04
4.6
Max
—
0.8
—
0.35
10
1
12
2.5
0.5
5.00
Unit
V
V
V
V
µA
mA
mA
mA
I
O
= –2 mA
I
O
= 2 mA
2.4
—
–10
V
A
pin
V
D
pin
PDN = 1, PDL = 0
PDN = 1, PDL = 1
Charge Pump On
—
—
—
—
4.3
V
Notes:
1.
Only a decoupling capacitor should be connected to V
A
when the charge pump is on.
2.
There is no I
A
current consumption when the internal charge pump is enabled and only a decoupling cap is connected
to the V
A
pin.
3.
All inputs at 0.4 or V
D
– 0.4 (CMOS levels). All inputs held static except clock and all outputs unloaded
(Static I
OUT
= 0 mA).
4.
RGDT is not functional in this state.
5.
The charge pump is recommended to be used only when V
D
< 4.5 V. When the charge pump is not used, V
A
should be
applied to the device before V
D
is applied on power up if driven from separate supplies.
Rev. 1.2
5
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