Thermoelectric Cooler Controller
ADN8830
FEATURES
High Efficiency
Small Size: 5 mm 5 mm LFCSP
Low Noise: <0.5% TEC Current Ripple
Long-Term Temperature Stability: 0.01 C
Temperature Lock Indication
Temperature Monitoring Output
Oscillator Synchronization with an External Signal
Clock Phase Adjustment for Multiple Controllers
Programmable Switching Frequency up to 1 MHz
Thermistor Failure Alarm
Maximum TEC Voltage Programmability
APPLICATIONS
Thermoelectric Cooler (TEC) Temperature Control
Resistive Heating Element Control
Temperature Stabilization Substrate (TSS) Control
GENERAL DESCRIPTION
The ADN8830 is a monolithic controller that drives a thermo-
electric cooler (TEC) to stabilize the temperature of a laser diode
or a passive component used in telecommunications equipment.
This device relies on a negative temperature coefficient (NTC)
thermistor to sense the temperature of the object attached to the
TEC. The target temperature is set with an analog input voltage
either from a DAC or an external resistor divider.
The loop is stabilized by a PID compensation amplifier with
high stability and low noise. The compensation network can be
adjusted by the user to optimize temperature settling time. The
component values for this network can be calculated based on
the thermal transfer function of the laser diode or obtained
from the lookup table given in the Application Notes section.
Voltage outputs are provided to monitor both the temperature of
the object and the voltage across the TEC. A voltage reference
of 2.5 V is also provided.
FUNCTIONAL BLOCK DIAGRAM
PID COMPENSATION
NETWORK
FROM
THERMISTOR
TEMPERATURE
SET
INPUT
V
REF
P-CHANNEL
(UPPER MOSFET)
TEMPERATURE
MEASUREMENT
AMPLIFIER
PWM
CONTROLLER
MOSFET
DRIVERS
P-CHANNEL
(LOWER MOSFET)
N-CHANNEL
N-CHANNEL
VOLTAGE
REFERENCE
OSCILLATOR
FREQUENCY/PHASE
CONTROL
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
ADN8830–SPECIFICATIONS
Parameter
TEMPERATURE STABILITY
Long-Term Stability
PWM OUTPUT DRIVERS
Output Transition Time
Nonoverlapping Clock Delay
Output Resistance
Output Voltage Swing
Output Voltage Ripple
Output Current Ripple
LINEAR OUTPUT AMPLIFIER
Output Resistance
Output Voltage Swing
POWER SUPPLY
Power Supply Voltage
Power Supply Rejection Ratio
Supply Current
Shutdown Current
Soft-Start Charging Current
Undervoltage Lockout
ERROR AMPLIFIER
Input Offset Voltage
Gain
Input Voltage Range
Common-Mode Rejection Ratio
Open-Loop Input Impedance
Gain-Bandwidth Product
REFERENCE VOLTAGE
Reference Voltage
OSCILLATOR
Synchronization Range
Oscillator Frequency
LOGIC CONTROL*
Logic Low Input Threshold
Logic High Input Threshold
Logic Low Output Level
Logic High Output Threshold
Symbol
(@ V
DD
= 3.3 V to 5.0 V, V
GND
= 0 V, T
A
= 25 C, T
SET
= 25 C, using typical application
configuration as shown in Figure 1, unless otherwise noted.)
Min
Typ
Max
Unit
Conditions
Using 10 kΩ thermistor with
= –4.4% at 25°C
0.01
20
65
6
V
DD
0.2
0.2
85
178
0
3.0
80
60
V
DD
5.5
92
8
5
15
2.0
50
20
0.2
58
55
68
1
2
12
15
°C
ns
ns
Ω
V
%
%
Ω
Ω
V
V
dB
dB
mA
mA
µA
µA
V
µV
V/V
V
dB
dB
GΩ
MHz
V
kHz
kHz
t
R
, t
F
R
O
(N1, P1)
OUT A
OUT A
I
TEC
R
O, P2
R
O, N2
OUT B
V
DD
PSRR
I
SY
I
SD
I
SS
V
OLOCK
V
OS
A
V, IN
V
CM
CMRR
R
IN
GBW
V
REF
f
CLK
f
CLK
C
L
= 3,300 pF
50
I
L
= 50 mA
V
LIM
= 0 V
f
CLK
= 1 MHz
f
CLK
= 1 MHz
I
OUT
= 2 mA
I
OUT
= 2 mA
0
V
DD
= 3.3 V to 5 V, V
TEC
= 0 V
–40°C
≤
T
A
≤
+85°C
PWM not switching
–40°C
≤
T
A
≤
+85°C
Pin 10 = 0 V
Low-to-high threshold
V
CM
= 1.5 V
0.2 V < V
CM
< 2.0 V
–40°C
≤
T
A
≤
+85°C
2.7
250
2.0
I
REF
< 2 mA
Pin 25 connected to external clock
Pin 24 = V
DD
; (R = 150 kΩ;
Pin 25 = GND)
2.37
200
800
2.47
2.57
1,000
1,250
1,000
0.2
3
0.2
V
DD
– 0.2
V
V
V
V
*Logic
inputs meet typical CMOS I/O conditions for source/sink current (~1
µA).
Specifications subject to change without notice.
–2–
REV. C
ADN8830
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . GND to V
S
+ 0.3 V
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . 125°C
Lead Temperature Range (Soldering, 10 sec) . . . . . . . . 300°C
ESD RATINGS
Package Type
32-Lead LFCSP (ACP)
JA
*
JC
Unit
°C/W
35
10
*
JA
is specified for worst-case conditions, i.e.,
JA
is specified for a device
soldered in a 4-layer circuit board for surface-mount packages.
883 (Human Body) Model . . . . . . . . . . . . . . . . . . . . . . 1.0 kV
*Stresses
above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model
ADN8830ACP
ADN8830ACP-REEL
ADN8830ACP-REEL7
ADN8830-EVAL
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package Description
32-Lead Lead Frame Chip Scale Package (LFCSP)
32-Lead Lead Frame Chip Scale Package (LFCSP)
32-Lead Lead Frame Chip Scale Package (LFCSP)
Evaluation Board
Package Option
CP-32-1
CP-32-1
CP-32-1
PIN CONFIGURATION
32 NC
31 TEMPOUT
30 AGND
29 PHASE
28 SYNCOUT
27 SOFTSTART
26 FREQ
25 SYNCIN
THERMFAULT 1
THERMIN 2
SD
3
TEMPSET 4
TEMPLOCK 5
NC 6
VREF 7
AVDD 8
PIN 1
INDICATOR
ADN8830
TOP VIEW
24 COMPOSC
23 PGND
22 N1
21 P1
20 PVDD
19 OUT A
18 COMPSWIN
17 COMPSWOUT
NC = NO CONNECT
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADN8830 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV. C
OUT B 9
N2 10
P2 11
TEMPCTL 12
COMPFB 13
COMPOUT 14
VLIM 15
VTEC 16
–3–
ADN8830
PIN FUNCTION DESCRIPTIONS
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Mnemonic
THERMFAULT
THERMIN
SD
TEMPSET
TEMPLOCK
NC
VREF
AVDD
OUT B
N2
P2
TEMPCTL
COMPFB
COMPOUT
VLIM
VTEC
Type
Digital Output
Analog Input
Digital Input
Analog Input
Digital Output
Description
Indicates an Open or Short-Circuit Condition from Thermistor.
Thermistor Feedback Input.
Puts Device into Low Current Shutdown Mode. Active low.
Target Temperature Input.
Indicates when Thermistor Temperature is within
±
0.1°C of Target Tem-
perature as Set by TEMPSET Voltage.
No Connection, except as Noted in the Application Notes Section.
2.5 V Reference Voltage.
Power for Nondriver Sections. 3.0 V min; 5.5 V max.
Linear Output Feedback. Will typically connect to TEC+ pin of TEC.
Drives Linear Output External NMOS Gate.
Drives Linear Output External PMOS Gate.
Output of Error Amplifier. Connects to COMPFB through feedforward
section of compensation network.
Feedback Summing Node of Compensation Amplifier. Connects to
TEMPCTL and COMPOUT through compensation network.
Output of Compensation Amplifier. Connects to COMPFB through feed-
back section of compensation network.
Sets Maximum Voltage across TEC.
Indicates Relative Voltage across the TEC. The 1.5 V corresponds to 0 V
across TEC. The 3.0 V indicates maximum output voltage, maximum heat
transfer through TEC.
Compensation for Switching Amplifier.
Compensation for Switching Amplifier. Capacitor connected between
COMPSWIN and COMPSWOUT.
PWM Output Feedback. Will typically connect to TEC– pin of TEC.
Power for Output Driver Sections. 3.0 V min; 5.5 V max.
Drives PWM Output External PMOS Gate.
Drives PWM Output External NMOS Gate.
Power Ground. External NMOS devices connect to PGND. Can be
connected to digital ground as noise sensitivity at this node is not critical.
Connect as Indicated in the Application Notes Section.
Optional Clock Input. If not connected, clock frequency set by FREQ pin.
Sets Switching Frequency.
Controls Initialization Time for ADN8830 with Capacitor to Ground.
Phase Adjusted Clock Output. Phase set from PHASE pin. Can be used to
drive SYNCIN of other ADN8830 devices.
Sets Switching and SYNCOUT Clock Phase Relative to SYNCIN Clock.
Analog Ground. Should be low noise for highest accuracy.
Indication of Thermistor Temperature.
No Connection.
Analog Output
Power
Analog Input
Analog Output
Analog Output
Analog Output
Analog Input
Analog Output
Analog Input
Analog Output
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
COMPSWOUT
COMPSWIN
OUT A
PVDD
P1
N1
PGND
COMPOSC
SYNCIN
FREQ
SOFTSTART
SYNCOUT
PHASE
AGND
TEMPOUT
NC
Analog Output
Analog Input
Analog Input
Power
Digital Output
Digital Output
Ground
Analog Input
Digital Input
Analog Input
Analog Input
Digital Output
Analog Input
Ground
Analog Output
–4–
REV. C
Typical Performance Characteristics–ADN8830
360
V
DD
= 5V
T
A
= 25 C
P1
PHASE SHIFT (Degrees)
320
280
240
200
160
120
80
40
SYNC IN = 200kHz
T
A
= 25 C
VOLTAGE (1V/DIV)
N1
0
0
0
0
0
0
0
0
TIME (20ns/DIV)
0
0
0
0
0
0
0.4
0.8
1.2
VPHASE (V)
1.6
2.0
2.4
TPC 1. N1 and P1 Rise Time
TPC 4. Clock Phase Shift vs. Phase Voltage
2.480
V
DD
= 5V
T
A
= 25 C
P1
2.475
VOLTAGE (1V/DIV)
V
REF
( V)
N1
0
0
0
0
0
0
0
0
TIME (20ns/DIV)
0
0
0
0
2.470
2.465
2.460
2.455
–40
–15
10
35
TEMPERATURE ( C)
60
85
TPC 2. N1 and P1 Fall Time
TPC 5. V
REF
vs. Temperature
360
320
280
PHASE SHIFT (Degrees)
1,000
SYNC IN = 1MHz
T
A
= 25 C
V
DD
= 5V
T
A
= 25 C
SWITCHING FREQUENCY (kHz)
800
240
200
160
120
80
40
0
0
600
400
200
0
0.4
0.8
1.2
VPHASE (V)
1.6
2.0
2.4
0
250
500
750
1,000
R
FREQ
(k )
1,250
1,500
TPC 3. Clock Phase Shift vs. Phase Voltage
TPC 6. Switching Frequency vs. R
FREQ
REV. C
–5–
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