NTLTD7900N
Power MOSFET
8.5 A, 20 V, Logic Level, N−Channel
Micro8] Leadless
EZFETs™ are an advanced series of Power MOSFETs which
contain monolithic back−to−back zener diodes. These zener diodes
provide protection against ESD and unexpected transients. These
miniature surface mount MOSFETs feature ultra low R
DS(on)
and true
logic level performance. EZFET devices are designed for use in low
voltage, high speed switching applications where power efficiency is
important. Typical applications are dc−dc converters, and power
management in portable and battery powered products such as
computers, printers, cellular and cordless phones.
Applications
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V
(BR)DSS
20 V
R
DS(on)
TYP
20 mW @ 4.5 V
22 mW @ 2.5 V
I
D
MAX
8.5 A
D
D
•
Zener Protected Gates Provide Electrostatic Discharge Protection
•
Designed to Withstand 4000 V Human Body Model
•
Ultra Low R
DS(on)
Provides Higher Efficiency and Extends
•
•
•
•
Battery Life
Logic Level Gate Drive − Can be Driven by Logic ICs
Micro8 Leadless Surface Mount Package − Saves Board Space
I
DSS
Specified at Elevated Temperature
Pb−Free Package is Available*
G
1
2.4 kW
G
2
2.4 kW
S
1
N−Channel
N−Channel
S
2
MAXIMUM RATINGS
(T
J
= 25°C unless otherwise noted)
Rating
Drain−to−Source Voltage
Gate−to−Source Voltage
Continuous Drain Current (Note 1)
T
A
= 25°C
T
A
= 85°C
Pulsed Drain Current
(tp
v
600
ms)
Continuous Source−Diode
Conduction (Note 1)
Total Power Dissipation (Note 1)
T
A
= 25°C
T
A
= 85°C
Operating Junction and Storage
Temperature Range
Thermal Resistance (Note 1)
Junction−to−Ambient
Symbol
V
DSS
V
GS
I
D
8.5
6.1
I
DM
I
s
P
D
3.1
1.6
T
J
, T
stg
R
qJA
1.5
0.79
°C
°C/W
2.9
30
1.4
6.0
4.2
A
A
W
10 Secs
20
±12
Steady
State
Unit
V
V
A
A
Y
WW
G
1
Micro8 Leadless
CASE 846C
MARKING DIAGRAM
1
790N
AYWW
G
= Assembly Location
= Year
= Work Week
= Pb−Free Package
PIN ASSIGNMENT
Drain
Drain
Drain
Drain
8
7
1
2
Source 1
Gate 1
Source 2
Gate 2
−55 to 150
40
82
Drain
6
5
3
4
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. When surface mounted to 1″ x 1″ FR−4 board.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
(Bottom View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
©
Semiconductor Components Industries, LLC, 2005
1
October, 2005 − Rev. 1
Publication Order Number:
NTLTD7900N/D
NTLTD7900N
ELECTRICAL CHARACTERISTICS
(T
J
= 25°C unless otherwise noted)
Characteristic
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage (Note 2)
(V
GS
= 0 Vdc, I
D
= 250
mAdc)
Zero Gate Voltage Drain Current
(V
DS
= 16 Vdc, V
GS
= 0 Vdc)
(V
DS
= 16 Vdc, V
GS
= 0 Vdc, T
J
= 85°C)
Gate−Body Leakage Current
(V
GS
=
"4.5
Vdc, V
DS
= 0 Vdc)
(V
GS
=
"12
Vdc, V
DS
= 0 Vdc)
ON CHARACTERISTICS
(Note 2)
Gate Threshold Voltage (Note 2)
(V
DS
= V
GS
, I
D
= 250
mAdc)
Static Drain−to−Source On−Resistance (Note 2)
(V
GS
= 4.5 Vdc, I
D
= 6.5 Adc)
(V
GS
= 2.5 Vdc, I
D
= 5.8 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Transfer Capacitance
SWITCHING CHARACTERISTICS
(Note 3)
Gate Charge
(V
GS
= 4.5 Vdc, I
D
= 6.5 Adc,
V
DS
= 10 Vdc)
(Note 2)
Q
T
Q
1
Q
2
t
d(on)
(V
GS
= 4.5 Vdc, V
DD
= 10 Vdc,
I
D
= 1.0 Adc, R
G
= 9.1
W)
(Note 2)
t
r
t
d(off)
t
f
−
−
−
−
−
−
−
12.4
1.3
3.5
0.55
1.17
2.9
3.8
16
−
−
1.1
2.2
5.8
7.7
ms
nC
(V
DS
= 16 Vdc, V
GS
= 0 V,
f = 10 kHz)
C
iss
C
oss
C
rss
−
−
−
785
135
100
−
−
−
pF
V
GS(th)
0.4
R
DS(on)
−
−
20
22
26
31
−
0.9
mW
Vdc
V
(BR)DSS
20
I
DSS
−
−
I
GSS
−
−
−
−
1.0
500
−
−
1.0
20
mAdc
−
−
mAdc
Vdc
Symbol
Min
Typ
Max
Unit
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
(I
S
= 1.5 Adc, V
GS
= 0 Vdc)
I
S
= 1.5 Adc, V
GS
= 0 Vdc, T
J
= 85°C)
(Note 2)
V
SD
−
−
0.65
0.60
1.0
−
Vdc
2. Pulse Test: Pulse Width
•
300
ms,
Duty Cycle
•
2%.
3. Switching characteristics are independent of operating junction temperatures.
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NTLTD7900N
TYPICAL ELECTRICAL CHARACTERISTICS
30
25
20
1.7 V
15
10
5
1.1 V
0
0
1
2
3
4
5
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
0
0
1
30
T
J
= 25°C
I
D
, DRAIN CURRENT (A)
V
GS
= 2 V
25
20
15
10
5
T
J
= 125°C
T
J
= 25°C
T
J
= −55°C
2
3
4.5 V
3.5 V
2.5 V
V
DS
≥
10 V
I
D
, DRAIN CURRENT (A)
1.4 V
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
R
DS(on)
, DRAIN−TO−SOURCE RESISTANCE (W)
R
DS(on)
, DRAIN−TO−SOURCE RESISTANCE (W)
0.07
0.06
0.05
0.04
0.03
0.02
0.01
1
2
3
4
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
I
D
= 8.5 A
T = 25°C
0.04
Figure 2. Transfer Characteristics
T
J
= 25°C
0.03
V
GS
= 2.5 V
0.02
V
GS
= 4.5 V
0.01
0
0
5
10
15
20
25
30
I
D
, DRAIN CURRENT (A)
Figure 3. On−Resistance versus Gate Voltage
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
100000
R
DS(on)
, DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
1.6
I
D
= 8.5 A
V
GS
= 4.5 V
V
GS
= 0 V
1.4
I
DSS
, LEAKAGE (nA)
10000
T
J
= 150°C
1.2
1
1000
T
J
= 125°C
0.8
0.6
−50
100
−25
0
25
50
75
100
125
150
0
5
10
15
20
T
J
, TEMPERATURE (°C)
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
versus Voltage
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3
NTLTD7900N
TYPICAL ELECTRICAL CHARACTERISTICS
T
J
= 25°C
V
GS
= 0 V
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
1400
1200
C, CAPACITANCE (pF)
1000
800
600
400
200
0
0
C
RSS
5
10
15
20
C
OSS
C
ISS
5
Q
T
4
3 Q
gs
Q
gd
2
1
0
0
2
4
6
8
10
Q
g
, TOTAL GATE CHARGE (nC)
I
D
= 6.5 A
T
J
= 25°C
12
14
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (V)
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and
Drain−to−Source Voltage versus Total Charge
10000
V
DD
= 10 V
I
D
= 1.0 A
V
GS
= 4.5 V
t, TIME (ns)
1000
t
f
t
d(off)
t
r
t
d(on)
3
V
GS
= 0 V
T
J
= 25°C
I
S
, SOURCE CURRENT (A)
2
100
1
10
1
10
R
G
, GATE RESISTANCE (W)
100
0
0
0.2
0.4
0.6
0.8
V
SD
, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
Figure 10. Diode Forward Voltage versus
Current
r(t), EFFECTIVE TRANSIENT
THERMAL RESISTANCE (NORMALIZED)
1
D = 0.5
0.2
0.1
0.05
0.02
SINGLE PULSE
0.01
10−4
10−3
10−2
10−1
t, TIME (seconds)
1
10
100
1000
P
(pk)
t
2
DUTY CYCLE, D = t
1
/t
2
t
1
R
qJC
(t) = r(t) R
qJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
1
T
J(pk)
− T
C
= P
(pk)
R
qJC
(t)
0.1
Figure 11. Thermal Response
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4
NTLTD7900N
ORDERING INFORMATION
Device
NTLTD7900NR2G
Package
Micro8 LL
(Pb−Free)
Shipping
†
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
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