MC14017B
Decade Counter
The MC14017B is a five−stage Johnson decade counter with
built−in code converter. High speed operation and spike−free outputs
are obtained by use of a Johnson decade counter design. The ten
decoded outputs are normally low, and go high only at their
appropriate decimal time period. The output changes occur on the
positive−going edge of the clock pulse. This part can be used in
frequency division applications as well as decade counter or decimal
decode display applications.
Features
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Fully Static Operation
DC Clock Input Circuit Allows Slow Rise Times
Carry Out Output for Cascading
Divide−by−N Counting
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range
Pin−for−Pin Replacement for CD4017B
Triple Diode Protection on All Inputs
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
This Device is Pb−Free and is RoHS Compliant
SOIC−16
D SUFFIX
CASE 751B
PIN ASSIGNMENT
Q5
Q1
Q0
Q2
Q6
Q7
Q3
V
SS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
RESET
CLOCK
CE
C
out
Q9
Q4
Q8
MAXIMUM RATINGS
(Voltages Referenced to V
SS
)
Symbol
V
DD
V
in
, V
out
I
in
, I
out
P
D
T
A
T
stg
T
L
Parameter
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Input or Output Current
(DC or Transient) per Pin
Power Dissipation, per Package
(Note 1)
Ambient Temperature Range
Storage Temperature Range
Lead Temperature
(8−Second Soldering)
Value
−0.5 to +18.0
−0.5 to V
DD
+ 0.5
±10
500
−55 to +125
−65 to +150
260
Unit
V
V
mA
mW
°C
°C
°C
MARKING DIAGRAM
16
14017BG
AWLYWW
1
A
WL, L
YY, Y
WW, W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Indicator
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
≤
(V
in
or V
out
)
≤
V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V
SS
or V
DD
). Unused outputs must be left open.
©
Semiconductor Components Industries, LLC, 2014
1
August, 2014 − Rev. 9
Publication Order Number:
MC14017B/D
MC14017B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS
(Voltages Referenced to V
SS
)
V
DD
Vdc
5.0
10
15
5.0
10
15
5.0
10
15
“1” Level
(V
O
= 0.5 or 4.5 Vdc)
(V
O
= 1.0 or 9.0 Vdc)
(V
O
= 1.5 or 13.5 Vdc)
Output Drive Current
(V
OH
= 2.5 Vdc)
(V
OH
= 4.6 Vdc)
(V
OH
= 9.5 Vdc)
(V
OH
= 13.5 Vdc)
(V
OL
= 0.4 Vdc)
(V
OL
= 0.5 Vdc)
(V
OL
= 1.5 Vdc)
Input Current
Input Capacitance
(V
in
= 0)
Quiescent Current
(Per Package)
Total Supply Current (Notes 3 & 4)
(Dynamic plus Quiescent,
Per Package)
(C
L
= 50 pF on all outputs, all
buffers switching)
I
OH
Source
5.0
5.0
10
15
I
OL
5.0
10
15
15
−
5.0
10
15
5.0
10
15
–3.0
–0.64
–1.6
–4.2
0.64
1.6
4.2
−
−
−
−
−
−
−
−
−
−
−
−
±0.1
−
5.0
10
20
–2.4
–0.51
–1.3
–3.4
0.51
1.3
3.4
−
−
−
−
−
–4.2
–0.88
–2.25
–8.8
0.88
2.25
8.8
±0.00001
5.0
0.005
0.010
0.015
−
−
−
−
−
−
−
±0.1
7.5
5.0
10
20
–1.7
–0.36
–0.9
–2.4
0.36
0.9
2.4
−
−
−
−
−
−
−
−
−
−
−
−
±1.0
−
150
300
600
mAdc
V
IH
5.0
10
15
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
mAdc
−55_C
25_C
125_C
Characteristic
Symbol
V
OL
Min
−
−
−
4.95
9.95
14.95
−
−
−
Max
Min
−
−
−
4.95
9.95
14.95
−
−
−
Typ
(Note 2)
0
0
0
5.0
10
15
2.25
4.50
6.75
Max
Min
−
−
−
4.95
9.95
14.95
−
−
−
Max
Unit
Vdc
Output Voltage
V
in
= V
DD
or 0
“0” Level
0.05
0.05
0.05
−
−
−
1.5
3.0
4.0
0.05
0.05
0.05
−
−
−
1.5
3.0
4.0
0.05
0.05
0.05
−
−
−
1.5
3.0
4.0
Vdc
“1” Level
V
in
= 0 or V
DD
Input Voltage
(V
O
= 4.5 or 0.5 Vdc)
(V
O
= 9.0 or 1.0 Vdc)
(V
O
= 13.5 or 1.5 Vdc)
“0” Level
V
IL
V
OH
Vdc
Vdc
Sink
I
in
C
in
I
DD
mAdc
pF
mAdc
I
T
I
T
= (0.27
mA/kHz)
f + I
DD
I
T
= (0.55
mA/kHz)
f + I
DD
I
T
= (0.83
mA/kHz)
f + I
DD
mAdc
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF:
I
T
(C
L
) = I
T
(50 pF) + (C
L
– 50) Vfk
where: I
T
is in
mA
(per package), C
L
in pF, V = (V
DD
– V
SS
) in volts, f in kHz is input frequency, and k = 0.0011.
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MC14017B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS
(Note 5) (C
L
= 50 pF, T
A
= 25_C)
Characteristic
Symbol
t
TLH
,
t
THL
V
DD
Vdc
5.0
10
15
Min
−
−
−
Typ
(Note 6)
100
50
40
Max
200
100
80
ns
5.0
10
15
t
PLH
,
t
PHL
5.0
10
15
t
PLH
,
t
PHL
5.0
10
15
t
PLH
5.0
10
15
t
w(H)
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
350
150
115
420
200
140
−
−
−
250
100
75
−
−
−
500
250
190
750
275
210
400
175
125
125
50
35
5.0
12
16
250
125
95
375
135
105
No Limit
175
75
52
260
100
70
−
−
−
−
−
−
ns
800
350
250
−
−
−
2.0
5.0
6.7
−
−
−
−
−
−
ns
−
−
−
500
230
175
1000
460
350
ns
−
−
−
400
175
125
800
350
250
ns
−
−
−
500
230
175
1000
460
350
ns
Unit
ns
Output Rise and Fall Time
t
TLH
, t
THL
= (1.5 ns/pF) C
L
+ 25 ns
t
TLH
, t
THL
= (0.75 ns/pF) C
L
+ 12.5 ns
t
TLH
, t
THL
= (0.55 ns/pF) C
L
+ 9.5 ns
Propagation Delay Time
Reset to Decode Output
t
PLH
, t
PHL
= (1.7 ns/pF) C
L
+ 415 ns
t
PLH
, t
PHL
= (0.66 ns/PF) C
L
+ 197 ns
t
PLH
, t
PHL
= (0.5 ns/pF) C
L
+ 150 ns
Propagation Delay Time
Clock to C
out
t
PLH
, t
PHL
= (1.7 ns/pF) C
L
+ 315 ns
t
PLH
, t
PHL
= (0.66 ns/pF) C
L
+ 142 ns
t
PLH
, t
PHL
= (0.5 ns/pF) C
L
+ 100 ns
Propagation Delay Time
Clock to Decode Output
t
PLH
, t
PHL
= (1.7 ns/pF) C
L
+ 415 ns
t
PLH
, t
PHL
= (0.66 ns/pF) C
L
+ 197 ns
t
PLH
, t
PHL
= (0.5 ns/pF) C
L
+ 150 ns
Turn−Off Delay Time
Reset to C
out
t
PLH
= (1.7 ns/pF) C
L
+ 315 ns
t
PLH
= (0.66 ns/pF) C
L
+ 142 ns
t
PLH
= (0.5 ns/pF) C
L
+ 100 ns
Clock Pulse Width
t
PLH
,
t
PHL
Clock Frequency
f
cl
MHz
Reset Pulse Width
t
w(H)
ns
Reset Removal Time
t
rem
ns
Clock Input Rise and Fall Time
t
TLH
,
t
THL
t
su
−
Clock Enable Setup Time
Clock Enable Removal Time
t
rem
ns
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
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