Si
I
161A PanelLink
®
Receiver
Datasheet
General Description
The SiI 161A receiver uses PanelLink Digital technology to support high
resolution displays up to UXGA. The SiI 161A receiver supports up to true
color panels (24 bit/pixel, 16.7M colors) in 1 or 2 pixels/clock mode. In
addition, the receiver data output is time staggered to reduce ground bounce
that affects EMI. Since all PanelLink products are designed on scaleable
CMOS architecture to support future performance requirements while
maintaining the same logical interface, system designers can be assured that
the interface will be fixed through a number of technology and performance
generations.
PanelLink Digital technology simplifies PC and display interface design
by resolving many of the system level issues associated with high-speed
mixed signal design, providing the system designer with a digital interface
solution that is quicker to market and lower in cost.
March 2001
Features
•
•
•
•
•
§
Low Power: 3.3V core operation
Time staggered data output for reduced ground
bounce
Sync Detect: for Plug & Display “Hot Plugging”
Cable Distance Support: over 5m with twisted-pair,
fiber-optics ready
Compliant with DVI 1.0 (DVI is backwards
compatible with VESA
®
P&D
T M
and DFP)
Supports Dual-Link operation up to 330 Mega-
pixels/second
CONTROLS
HSYNC
VSYNC
OGND
OUTPUT CLOCK
Si
I
161
A Pin Diagram
GPO
OVCC
QE23
CTL3
CTL2
CTL1
GND
VCC
EVEN 8-bits RED
OGND
OVCC
QE22
QE21
QE20
QE19
QE18
QE17
QE16
QE15
QE14
ODCK
QO1
QO0
DE
ODD 8-bits BLUE
QO2
QO3
QO4
QO5
QO6
QO7
OVCC
OGND
QO8
QO9
QO10
QO11
QO12
QO13
QO14
QO15
VCC
GND
QO16
QO17
QO18
QO19
QO20
QO21
QO22
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
100
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
QE13
QE12
QE11
QE10
QE9
QE8
OGND
OVCC
QE7
QE6
QE5
QE4
QE3
QE2
QE1
QE0
PDO
SCDT
VCC
GND
SiI 161A
100-Pin TQFP
(Top View)
STAG_OUT/SYNC
ODD 8-bits RED
PIXS/M_S
ST
PD
S_D
DIFFERENTIALSIGNAL
PLL
Silicon Image, Inc.
Subject to Change without Notice
RESERVED
OCK_INV
EXT_RES
CONFIG. PINS
OGND
AGND
AGND
AGND
AGND
AGND
OVCC
AVCC
AVCC
AVCC
AVCC
PGND
QO23
RX2+
RX1+
RX0+
RX2-
RX1-
RX0-
PVCC
RXC+
RXC-
EVEN 8-bits BLUE
PWR
MANAGEMENT
ODD 8-bits GREEN
EVEN 8-bits GREEN
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
Silicon Image, Inc.
Functional Block Diagram
PIXS
DF0
OCK_INV
EXT_RES
Termination
Control
Data Recovery
SYNC2
CH2
Data Recovery
SYNC1
CH1
Data Recovery
SYNC0
CH0
SiI 161
A
SiI
-DS-0009-D
RX2+
RX2-
RX1+
RX1-
RX0+
RX0-
RXC+
RXC-
PDO
STAG_OUT
ST
VCR
SYNC2
DATA
CTL3
CTL2
DATA
Decoder CTL1
DATA
VSYNC
HSYNC
Panel
Inter-
face
Logic
24
24
VCR
Channel
SYNC SYNC1
VCR
SYNC0
QE[23:0]
QO[23:0]
ODCK
DE
HSYNC
VSYNC
SCDT
CTL1
CTL2
CTL3
VCR
PLL
Absolute Maximum Conditions
Symbol
Parameter
V
CC
Supply Voltage 3.3V
V
I
Input Voltage
V
O
T
A
T
STG
θ
JA
1
Min
-0.3
-0.3
-0.3
-25
-65
Typ
Output Voltage
Ambient Temperature (with power
applied)
Storage Temperature
Thermal Resistance (Junction to
Ambient)
Max
4.0
V
CC
+
0.3
V
CC
+
0.3
105
150
Units
V
V
V
°C
°C
°C/W
21
Notes: Permanent device damage may occur if absolute maximum conditions are exceeded.
2
Functional operation should be restricted to the conditions described under Normal Operating Conditions.
Normal Operating Conditions
Symbol
Parameter
V
CC
Supply Voltage
V
CCN
Supply Voltage Noise
T
A
Ambient Temperature (with power
applied)
Min
3.0
0
Typ
3.3
25
Max
3.6
100
70
Units
V
mV
P-P
°C
Silicon Image, Inc.
2
Subject to Change without Notice
Silicon Image, Inc.
DC Digital I/O Specifications
SiI 161
A
SiI
-DS-0009-D
Under normal operating conditions unless otherwise specified.
Symbol
V
IH
V
IL
V
OH
V
OL
V
CINL
V
CIPL
V
CONL
V
COPL
I
OL
1
Parameter
High-level Input
Voltage
Low-level Input
Voltage
High-level Output
Voltage
Low-level Output
Voltage
Input Clamp Voltage
1
Input Clamp Voltage
1
Output Clamp
Voltage
1
Output Clamp
Voltage
1
Output Leakage
Current
Conditions
Min
2
Typ
Max
Units
V
V
V
0.8
2.4
0.4
I
CL
= -18mA
I
CL
= 18mA
I
CL
= -18mA
I
CL
= 18mA
High
Impedance
-10
GND -0.8
IVCC + 0.8
GND -0.8
OVCC + 0.8
10
V
V
V
V
V
µA
Note: Guaranteed by design. Voltage undershoot or overshoot cannot exceed absolute maximum conditions for a pulse of
greater than 3 ns or one third of the clock cycle.
DC Specifications
Under normal operating conditions unless otherwise specified.
Symbol
I
OHD
I
OLD
Parameter
Output High Drive Data and
Controls
Output Low Drive Data and
Controls
V
OUT
V
OUT
Conditions
= 2.4 V; ST = 1
ST = 0
= 0.8 V;
ST = 1
ST = 1
ST = 0
ST = 1
ST = 0
ST = 1
ST = 1
ST = 0
Min
4.2
2.1
-7
-5.2
-2.6
8.5
4.2
-15
-10.4
-5.2
75
Typ
8
4
-11
-5.5
-2.8
17
9
-20
-16
-8
Max
18
9
-15
-11
-5.5
37
18
-25
-23
-11
1000
1
270
Units
mA
mA
mA
mA
mA
mA
mV
mA
mA
V
OUT
= 0.4 V;
I
OHC
I
OLC
ODCK, DE High Drive
ODCK, DE Low Drive
V
OUT
= 2.4 V;
V
OUT
= 0.8V;
V
OUT
= 0.4 V;
V
ID
I
PD
I
CCR
Differential Input Voltage
Single Ended Amplitude
Power-down Current
2
Receiver Supply Current
I
PDO
Receiver Supply Current with
Ouputs Powered Down
ODCK=82.5MHz,
2-pixel/clock mode
C
LOAD
= 10pF
R
EXT_SWING
= 510Ω
Typical Pattern
3
ODCK=82.5MHz,
2-pixel/clock mode
C
LOAD
= 10pF
R
EXT_SWING
= 510Ω
Worst Case Pattern
4
ODCK=82.5MHz,
2-pixel/clock mode
C
LOAD
= 10pF
R
EXT_SWING
= 510Ω
Worst Case Pattern
4
240
270
330
mA
240
mA
Notes:
1
Guaranteed by design.
Silicon Image, Inc.
3
Subject to Change without Notice
Silicon Image, Inc.
AC Specifications
Under normal operating conditions unless otherwise specified.
SiI 161
A
SiI
-DS-0009-D
Symbol
T
DPS
T
CCS
T
IJIT
Parameter
Intra-Pair (+ to -) Differential Input Skew
1
Channel to Channel Differential Input Skew
1
Worst Case Differential Input Clock Jitter
tolerance
2,3
Low-to-High Transition Time: Data and Controls
(70 C, 82.5 MHz, 2-pixel/clock, PIXS=1)
D
LHT
Low-to-High Transition Time: Data and Controls
(70 C, 165 MHz, 1-pixel/clock, PIXS=0)
Low-to-High Transition Time: ODCK
(70 C, 82.5 MHz, 2-pixel/clock, PIXS=1)
Low-to-High Transition Time: ODCK
(70 C, 165 MHz, 1-pixel/clock, PIXS=0)
D
HLT
High-to-Low Transition Time: Data and Controls
(70 C, 82.5 MHz, 2-pixel/clock, PIXS=1)
High-to-Low Transition Time: Data and Controls
(70 C, 165 MHz, 1-pixel/clock, PIXS=0)
High-to-Low Transition Time: ODCK
(70 C, 82.5 MHz, 2-pixel/clock, PIXS=1)
High-to-Low Transition Time: ODCK
(70 C, 165 MHz, 1-pixel/clock, PIXS=0)
T
SETUP
Data, DE, VSYNC, HSYNC, and CTL[3:1] Setup
Time to ODCK falling edge (OCK_INV = 0) or to
ODCK rising edge (OCK_INV = 1) at 165 MHz
*OCK_INV = 1
Data, DE, VSYNC, HSYNC, and CTL[3:1] Hold Time
from ODCK falling edge, (OCK_INV = 0) or from
ODCK rising edge (OCK_INV = 1) at 165 MHz,
*OCK_INV = 0
1
2
3
4
5
Conditions
165MHz
165MHz
65 MHz
112 MHz
165 MHz
C
L
= 10pF;
ST = 1
C
L
= 5pF;
ST = 0
C
L
= 10pF;
ST = 1
C
L
= 5pF;
ST = 0
C
L
= 10pF;
ST = 1
C
L
= 5pF;
ST = 0
C
L
= 10pF;
ST = 1
C
L
= 5pF;
ST = 0
C
L
= 10pF;
ST = 1
C
L
= 5pF;
ST = 0
C
L
= 10pF;
ST = 1
C
L
= 5pF;
ST = 0
C
L
= 10pF;
ST = 1
C
L
= 5pF;
ST = 0
C
L
= 10pF;
ST = 1
C
L
= 5pF;
ST = 0
C
L
= 10pF;
ST = 1
C
L
= 5pF;
ST = 0
C
L
= 10pF;
ST = 1
C
L
= 5pF;
ST = 0
Min
Typ
Max
245
4
465
270
182
2.6
2.7
2.4
3.0
1.3
1.7
1.4
1.7
2.8
3.4
2.3
3.3
1.1
1.5
1.2
1.5
Units
ps
ns
ps
ps
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.7
*0.7
0.7
*0.4
3.8
*3.8
4.2
*3.8
ns
ns
T
HOLD
ns
Notes:
Guaranteed by design.
Jitter defined as per DVI 1.0 Specification, Section 4.6
Jitter Specification.
Jitter measured with Clock Recovery Unit as per DVI 1.0 Specification, Section 4.7
Electrical Measurement Procedures.
Output clock duty cycle is independent of the differential input clock duty cycle and the IDCK duty cycle.
Measured when transmitter was powered down (see SiI /AN-0005 “PanelLink Basic Design/Application Guide,” Section 2.4).
Silicon Image, Inc.
5
Subject to Change without Notice
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