AN1645
APPLICATION NOTE
STSR2P/STSR2PM SIMPLIFIES IMPLEMENTATION OF
SYNCHRONOUS RECTIFIERS IN FORWARD CONVERTER
F. Librizzi - F. Lentini
1. ABSTRACT
This paper describes the functionality and the operation of the STSR2P device used as the secondary
synchronous rectifier driver in Forward topology switched mode power supplies. A schematic and layout
description of a demo board, able to replace diode rectification with synchronous rectification in Forward
converters, is shown below.
Figure 1: Typical Application Schematic
Feedback
Loop
TRANSFORMER
INDUCTOR
Vin
MosfetN
Q2
Cout
Vout
MosfetN
Q1
1
8
7
100nF
2
PWM
bs
O
et
l
o
P
e
ro
uc
d
INHIBIT
s)
P
(
STSR2
t
D1
so
b
-O
OUTGate2
PWRGND
5
P
te
le
100nF
6
3
od
r
+5V
R1
s)
t(
uc
OUTGate1
SGLGND
Vcc
SETANT
R2
R3
Ck
4
R4
+5V
D3
R5
D2
option
+5V
2. GENERAL DEVICE DESCRIPTION
The STSR2P Smart Driver IC provides two complementary high current outputs to drive Power Mosfets.
The IC is dedicated to properly drive secondary Synchronous Rectifiers in medium power, low output
voltage, high efficiency Forward Converters. From a synchronizing clock input, the IC generates two
driving signals with a certain dead time between complementary pulses. The adopted transitions
December 2003 (rev.1)
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AN1645 - APPLICATION NOTE
revelation mechanism makes circuit operation independent by the forward magnetic reset technique
used, avoiding most of the common problems inherent in self-driven synchronous rectifiers. The IC
operation prevents secondary side shoot-through conditions providing proper timing at the outputs turn-
off transition. This smart function operates through a fast cycle-after-cycle control logic mechanism
based on an internal high frequency oscillator, synchronized by the clock signal. The IC provides a fixed
anticipation in turning-off the OUTGate1 with respect to the clock signal transition, while the anticipation
in turning-off the OUTGate2 can be set through external components. A special Inhibit function allows
the shut-off of one of the two outputs allowing operation during discontinuous conduction mode and
preventing the freewheeling mosfet from sinking current from the output.
The STSR2P automatically turns off the outputs when duty-cycle is lower than 13%, while STSR2PM
works even at very low duty-cycle values.
.
3. PIN CONNECTIONS AND DESCRIPTIONS
The STSR2P is housed in a SO-8 package for SMD assembly. Device pin out is shown in figure 2 and
table 1 briefly summarizes the device pin functionality.
Figure 2: Pin Configuration
Table 1: Pin Configuration
Pin Number
1
2
3
4
5
6
Pin Name
OUTGate1
Vcc
SETANT
2
O
7
8
so
b
te
le
ro
P
uc
d
s)
t(
so
b
-O
P
te
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od
r
s)
t(
uc
Pin Function
Supply input from 4V to 5.5V
Sets the anticipation in turning-off the OUT
GATE2
Output for Forward MOSFET Gate Drive
CK
INHIBIT
SGLGND
OUTGate2
PWRGND
Synchronization for IC’s operation
Discontinuous Mode Detector
Reference for all the control logic signals
Output for Freewheeling MOSFET Gate Drive
Reference for power signals
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AN1645 - APPLICATION NOTE
Figure 3: Block Schematic
4. SUPPLY VOLTAGE AND UNDER VOLTAGE LOCK-OUT
The supply input range is from 4V to 5.5V. An internal zener diode limits the maximum voltage to 5.7V.
A 100nF ceramic capacitor must be connected to Vcc and SGLGND pin in order to assure a stable
supply voltage. This capacitor must be placed very close to the device. Another 100nF capacitor is
necessary between Vcc and PWRGND.
Under Voltage Lock Out feature guarantees proper start-up while it avoids undesirable driving during
eventual dropping of the supply voltage.
As shown in the Block Diagram, the Vcc voltage also supplies the two output drivers, consequently the
maximum driving voltage is 5.5V, so the use of logic gate threshold mosfets is recommended.
5. SYNCHRONIZATION
O
An innovative feature of the STSR2P is the capability to operate in the secondary side without any
synchronization signal coming from the primary side. The IC synchronization is obtained directly from the
secondary side using the voltage across the free wheeling mosfet as the information for the switching
transitions. The Ck pin is the input for the synchronization signal; the internal threshold is set at 2.8V. As
can be seen in figure 3, a Peak Detector is present at the Ck pin. This block is able to distinguish
between the primary mosfet switching transitions and the eventual sinusoidal waveform caused by
discontinuous mode operation (see figure 4). A wrong synchronization causes wrong driving of the
synchronous rectifiers.
so
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t(
so
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P
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t(
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AN1645 - APPLICATION NOTE
Figure 4: DCM waveform
V
1
Peak
Detector
Input
On
Time
Off Time
Dead Time
Peak
Detector
Output
5.1 Continuous Conduction Mode
When the converter is working in continuous mode the voltage across the source and drain of the free
wheeling mosfet has a square shape. This voltage can be applied to the Ck pin using two different
configurations: with a resistor divider (figure 6) or with a diode and pull-up resistor (figure 7). In most
cases a spike is present during turn-off of the synchronous mosfet; this spike must be eliminated at the
Ck pin in order to avoid false synchronization.
Using the resistor divider, the spike is eliminated by adding a small capacitor (C1) as shown in figure 6.
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AN1645 - APPLICATION NOTE
Figure 5: CCM waveform and Ck circuit
Turn-Off
Spike
On Time
Off Time
In a typical Forward converter for telecom application, the DC input voltage has a 1:2 variability range
(typically 36V-72V). Consequently the secondary winding voltage has also 1:2 variability. The resistor
divider can be calculated in order to have about 2.8V at the Ck pin at 36V input; at 72V input, the Ck pin
reaches 5.6V. Even if this value is higher than the maximum voltage on the CK pin, it can be accepted
limiting the current flowing into the pin to 10mA.
Figure 6: Synchronization with a resistor divider
FREE WHEEL
OUTGate2
OUTGate1
PWRGND
O
so
b
te
le
ro
P
+5V
uc
d
D1
C1
s)
t(
R1
4
R2
6
so
b
-O
7
8
1
P
te
le
od
r
s)
t(
uc
FORWARD
+5V
Vcc
2
Ck
STSR2P
SETANT
3
SGLGND
INHIBIT
5
In case the Forward converter has a higher variability range 1:3 or 1:4, at minimum input voltage, 2.8V
must be guaranteed at the Ck pin. At maximum input voltage, the voltage at the Ck pin will be 7.5V or
10V. This voltage exceeds the absolute maximum ratings of the device. If R2 limits the current flowing
into the Ck pin to a value below the maximum Ck current value indicated in the datasheet (10mA), the
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