I
2
C Programmable Ethernet Clock
Generator
8T49N4811
DATA SHEET
General Description
The 8T49N4811I is a highly flexible FemtoClock
®
NG
pin-programmable clock generator suitable for networking and
communications applications. It is able to generate five different
output frequencies with multiple copies of each. A fundamental mode
crystal, single-ended, or differential input reference may be used as
the source for the output frequency.
The use of pin-programming to select the input source / frequency,
desired output frequencies and output styles allow a single device to
be used in a wide variety of applications without the need for register
programming.
Selection pins use 3-level options to maximize flexibility while
minimizing package size. Selection is performed by tying a selection
pin high or low or by leaving it floating, eliminating the need for
passive components to drive a desired logic level.
Features
•
•
•
•
•
•
•
•
•
Fourth generation FemtoClock
®
NG technology
Generates multiple copies of 25MHz, 50MHz, 100MHz, 125MHz,
156.25MHz or 312.5MHz
Typical input frequency is 25MHz, with optional 125MHz and
156.25MHz input support
Differential outputs are pin programmable for LVDS or LVPECL
RMS phase jitter at 156.25MHz: <300fs typical
Power Supply Rejection Ratio better than -50dBc from
10k-1.5MHz at 3.3V power supply
Full 3.3V and 2.5V Supply Voltages
-40°C to +85°C ambient operating temperature
56-pin VFQFPN, lead-free (RoHS 6) packaging
Block Diagram
2.5V ±5% or
3.3V
±10%
PLL Bypass
SDATA, SCLK
/A
IIC_ADRX_SEL
IN_SEL
XTAL_IN
0
1
Bank A
1
LVPECL/LVDS
125MHz/156.25MHz/312.5MHz
/B
0
1
Bank B
6
LVPECL/LVDS
50MHz/125MHz/156.25MHz
f
IN
XTAL_OUT
OSC
0
f
IN
APLL
/C
0
1
Bank C
2
LVPECL/LVDS
100MHz/125MHz/156.25MHz
DIN
100Ω
1
/D0
nDIN
SLEW_LVCMOS
LVCMOS_CTRL
Qx_CTRL
QB_CTRL [1:0]
INPUT_DIVSEL
DIVSEL_x
4
3
Frequency,
Output Type,
Slew
Rate, &
Output Enable
Control
Input Divider
Bank D0 1
LVPECL/LVDS
25MHz/125MHz/156.25MHz
/D1
Frequency
Select
Output Enable,Type, &
Slew
Rate Control
Bank D1 1
LVCMOS
25MHz/125MHz
8T49N4811 REVISION A 3/30/15
1
©2015 Integrated Device Technology, Inc.
8T49N4811 DATA SHEET
Pin Assignment
QB0
nQB0
QB1
nQB1
V
DD_OB
QB2
nQB2
QB3
nQB3
V
DD_OB
QB4
nQB4
QB5
nQB5
QB_CTRL0
V
DD
QA_CTRL
V
DD_OA
nQA0
QA0
DIVSEL_A
QC_CTRL
V
DD_OC
nQC1
QC1
nQC0
QC0
V
DD_OC
42 41 40
39 38 37 36 35 34 33 32 31 30
29
43
28
44
27
45
26
IDT8T49N4811I
46
25
56-Lead VFQFN
47
24
48
23
8mm x 8mm x 0.90mm
49
22
Package Body
50
21
5.9mm x 5.9mm ePad Size
51
20
NLG Suffix
52
19
Top View
53
18
54
17
55
16
56
15
1 2
3
4 5 6 7
8 9
10 11 12 13 14
DIVSEL_C
V
DD
IN_SEL
DIN
nDIN
V
DD_XTAL
XTAL_IN
XTAL_OUT
PLL_BYPASS
IIC_ADRX_SEL
V
DDA
INPUT_DIVSEL
DIVSEL_D0
LVCMOS_CTRL
SLEW_LVCMOS
V
DD
QB_CTRL1
V
DD_OD
QD0
nQD0
QD_CTRL
V
DD_ODS
QD0_S
nc
DIVSEL_B
Reserved
SDATA
SCLK
I
2
C PROGRAMMABLE ETHERNET CLOCK GENERATOR
2
REVISION A 3/30/15
8T49N4811 DATA SHEET
Pin Description and Pin Characteristic Tables
Table 1. Pin Description
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Name
DIVSEL_C
V
DD
IN_SEL
DIN
nDIN
V
DD_XTAL
XTAL_IN
XTAL_OUT
PLL_BYPASS
IIC_ADRX_SEL
V
DDA
INPUT_DIVSEL
DIVSEL_D0
LVCMOS_CTRL
SCLK
SDATA
Reserved
DIVSEL_B
nc
QD0_S
V
DD_ODS
QD_CTRL
nQD0
QD0
V
DD_OD
QB_CTRL1
V
DD
SLEW_LVCMOS
nQB5
QB5
nQB4
QB4
V
DD_OB
nQB3
Output
Power
Input
Output
Output
Power
Input
Power
Input
Output
Output
Output
Output
Power
Output
Pulldown
Pullup/Pulldown
Input
Input
Power
Input
Input
Input
Power
Input
Output
Input
Input
Power
Input
Input
Input
Input
I/O
Pullup/Pulldown
Pulldown
Pulldown
Type
Description
Pullup/Pulldown
Output divider selection for Bank C. LVCMOS interface levels.
Core supply.
Pullup/Pulldown
Input select between XTAL or differential input. LVCMOS interface levels.
Differential Reference Input. Accepts DC-coupled LVDS and is internally biased to
accept AC-coupled LVPECL, CML, HCSL or LVPECL signals. The differential
inputs have an internal 100 resistor biased to V
DD
–1.3V approximately.
Crystal oscillator power supply.
Crystal input.
Crystal output.
PLL Bypass. Provides copy of f
IN
to output banks A, B, C. LVCMOS interface
levels.
Selects between I
2
C addresses. LVCMOS interface levels.
Analog supply.
Selects proper divide ratios for differential reference input. LVCMOS interface
levels.
Pullup/Pulldown
Output divider selection for Bank D0 differential output. LVCMOS interface levels.
Pullup/Pulldown
Pullup
Pullup
Pulldown
Divider and output enable control for Bank D1 LVCMOS output. LVCMOS
interface levels.
I
2
C Clock Input. LVCMOS/LVTTL interface levels.
I
2
C Data Input/Output. Input: LVCMOS/LVTTL interface levels. Output: Open Drain.
Reserved. Internally connected to 50k pulldown.
Pullup/Pulldown
Output divider selection for Bank B. LVCMOS interface levels.
This pin is not internally connected. Connect to ground to maintain second source
compatibility.
Bank D1 LVCMOS Output.
Power supply for Bank D1 LVCMOS output.
Pullup/Pulldown
Control input for bank D0 output type and OE status. LVCMOS interface levels.
Bank D0 Differential Output. LVDS or LVPECL output levels.
Bank D0 Differential Output. LVDS or LVPECL output levels.
Power supply for Bank D0 differential output.
Control input for bank B outputs QB3 to QB5 output type and OE status. LVCMOS
interface levels.
Power supply.
Slew rate control pin for LVCMOS output. LVCMOS interface levels.
Bank B Differential Output. LVDS or LVPECL output levels.
Bank B Differential Output. LVDS or LVPECL output levels.
Bank B Differential Output. LVDS or LVPECL output levels.
Bank B Differential Output. LVDS or LVPECL output levels.
Power supply for Bank B.
Bank B Differential Output. LVDS or LVPECL output levels.
REVISION A 3/30/15
3
I
2
C PROGRAMMABLE ETHERNET CLOCK GENERATOR
8T49N4811 DATA SHEET
Table 1. Pin Description (Continued)
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
E-PAD
QB3
nQB2
QB2
V
DD_OB
nQB1
QB1
nQB0
QB0
QB_CTRL0
V
DD
QA_CTRL
V
DD_OA
nQA0
QA0
DIVSEL_A
QC_CTRL
V
DD_OC
nQC1
QC1
nQC0
QC0
V
DD_OC
GND
Output
Output
Output
Power
Output
Output
Output
Output
Input
Power
Input
Power
Output
Output
Input
Input
Power
Output
Output
Output
Output
Power
Power
Pullup/Pulldown
Bank B Differential Output. LVDS or LVPECL output levels.
Bank B Differential Output. LVDS or LVPECL output levels.
Bank B Differential Output. LVDS or LVPECL output levels.
Power supply for Bank B.
Bank B Differential Output. LVDS or LVPECL output levels.
Bank B Differential Output. LVDS or LVPECL output levels.
Bank B Differential Output. LVDS or LVPECL output levels.
Bank B Differential Output. LVDS or LVPECL output levels.
Control input for bank B outputs QB0 to QB2 output type and OE status. LVCMOS
interface levels.
Power supply.
Pullup/Pulldown
Control input for bank A output type and OE status. LVCMOS interface levels.
Power supply for Bank A.
Bank A Differential Output. LVDS or LVPECL output levels.
Bank A Differential Output. LVDS or LVPECL output levels.
Pullup/Pulldown
Output divider selection for Bank A. LVCMOS interface levels.
Pullup/Pulldown
Control input for bank C output type and OE status. LVCMOS interface levels.
Power supply for Bank C.
Bank C Differential Output. LVDS or LVPECL output levels.
Bank C Differential Output. LVDS or LVPECL output levels.
Bank C Differential Output. LVDS or LVPECL output levels.
Bank C Differential Output. LVDS or LVPECL output levels.
Power supply for Bank C.
Connect to ground; use thermal vias.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
Parameter
Input Capacitance
Input Pullup Resistor
SCLK, SDATA
DIVSEL_x, IN_SEL, IN_SEL,
INPUT_DIVSEL, LVCMOS_CTRL,
Qx_CTRL, QB_CTRL[1:0]
PLL_BYPASS, IIC_ADRX_SEL,
Reserved, SLEW_LVCMOS
V
DD
= V
DDO_ODS
= 3.63V
V
DD
= V
DDO_ODS
= 2.625V
V
DDO_ODS
= 3.3V
V
DDO_ODS
= 2.5V
Test Conditions
Minimum
Typical
3.5
50
58
42
50
18
16
24
30
Maximum
Units
pF
k
k
k
k
pF
pF
R
PULLDOWN
Input Pulldown Resistor
C
PD
R
OUT
Power Dissipation
Capacitance
Output
Impedance
QDO_S
QDO_S
QDO_S
QDO_S
I
2
C PROGRAMMABLE ETHERNET CLOCK GENERATOR
4
REVISION A 3/30/15
8T49N4811 DATA SHEET
Function Tables
Table 3A. Input Frequency Select Table
INPUT_DIVSEL
0
1
Float
25MHz
125MHz
156.25MHz
Table 3G. Bank C Frequency Select Table
DIVSEL_C
0
1
Float
Frequency
156.25MHz
125MHz
100MHz
Table 3B. Slew Rate Control Table
SLEW_LVCMOS
0 (default)
1
Normal
Slow
Table 3H. Bank D1 LVCMOS Control Table
LVCMOS_CTRL
0
1
Float
State
High Impedance
125MHz
f
IN
Table 3C. PLL Bypass Table
PLL_BYPASS
0 (default)
1
Normal Operation
PLL Bypassed
Table 3I. Bank D0 QD0 Frequency Select Table
DIVSEL_D0
0
1
Float
Frequency
156.25MHz
125MHz
f
IN
Table 3D. I
2
C Address Selection Table
IIC_ADRX_SEL
0 (default)
1
Address
DC (h)
DE (h)
Table 3J. Clock Select Function Table
Control Input
IN_SEL
0
1
Float
Clock
Crystal
Selected
De-selected
Selected
(Doubler = ON)
DIN, nDIN
De-selected
Selected
De-selected
Table 3E. Bank A Frequency Select Table
DIVSEL_A
0
1
Float
Frequency
156.25MHz
125MHz
312.5MHz
Table 3K. Qx_CTRL and QB_CTRL[1:0] Pin Table
Bank Mode Pin
Bank Mode
LVPECL
Selected; Note 1, 2
De-selected
High Impedance;
Note 3
LVDS
De-selected
Selected; Note 1, 2
High Impedance;
Note 3
Table 3F. Bank B Frequency Select Table
DIVSEL_B
0
1
Float
Frequency
156.25MHz
125MHz
50MHz
0
1
Float
NOTE 1: QD_CTRL affects differential outputs ONLY.
NOTE 2: QB_CTRL0 affects outputs QB[0:2]. QB_CTRL1 affects
outputs QB[3:5].
NOTE 3: High impedance mode: 100k pulldown on true output, 100k
pullup on compliment output.
REVISION A 3/30/15
5
I
2
C PROGRAMMABLE ETHERNET CLOCK GENERATOR
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
