74HC165; 74HCT165
8-bit parallel-in/serial out shift register
Rev. 03 — 14 March 2008
Product data sheet
1. General description
The 74HC165; 74HCT165 are high-speed Si-gate CMOS devices that comply with
JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL (LSTTL).
The 74HC165; 74HCT165 are 8-bit parallel-load or serial-in shift registers with
complementary serial outputs (Q7 and Q7) available from the last stage. When the
parallel load (PL) input is LOW, parallel data from the D0 to D7 inputs are loaded into the
register asynchronously.
When PL is HIGH, data enters the register serially at the DS input and shifts one place to
the right (Q0
→
Q1
→
Q2, etc.) with each positive-going clock transition. This feature
allows parallel-to-serial converter expansion by tying the Q7 output to the DS input of the
succeeding stage.
The clock input is a gated-OR structure which allows one input to be used as an active
LOW clock enable (CE) input. The pin assignment for the CP and CE inputs is arbitrary
and can be reversed for layout convenience. The LOW-to-HIGH transition of input CE
should only take place while CP HIGH for predictable operation. Either the CP or the CE
should be HIGH before the LOW-to-HIGH transition of PL to prevent shifting the data
when PL is activated.
2. Features
I
I
I
I
Asynchronous 8-bit parallel load
Synchronous serial input
Complies with JEDEC standard no. 7A
ESD protection:
N
HBM JESD22-A114E exceeds 2000 V
N
MM JESD22-A115-A exceeds 200 V
I
Specified from
−40 °C
to +85
°C
and from
−40 °C
to +125
°C
3. Applications
I
Parallel-to-serial data conversion
NXP Semiconductors
74HC165; 74HCT165
8-bit parallel-in/serial out shift register
4. Ordering information
Table 1.
Ordering information
Temperature range Name
74HC165N
74HCT165N
74HC165D
74HCT165D
74HC165DB
74HCT165DB
74HC165PW
74HCT165PW
74HC165BQ
74HCT165BQ
−40 °C
to +125
°C
−40 °C
to +125
°C
TSSOP16
−40 °C
to +125
°C
SSOP16
plastic shrink small outline package; 16 leads; body width
5.3 mm
plastic thin shrink small outline package; 16 leads; body
width 4.4 mm
SOT338-1
SOT403-1
SOT763-1
−40 °C
to +125
°C
SO16
plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
−40 °C
to +125
°C
DIP16
Description
plastic dual in-line package; 16 leads (300 mil)
Version
SOT38-4
Type number Package
DHVQFN16 plastic dual in-line compatible thermal enhanced very thin
quad flat package; no leads; 16 terminals; body
2.5
×
3.5
×
0.85 mm
5. Functional diagram
SRG8
C2[LOAD]
G1[SHIFT]
15
10
11
12
13
14
3
4
5
6
1
DS
D0
D1
D2
D3
D4
D5
D6
D7
PL
CP CE
2
15
mna985
mna986
1
≥
1
2
10
11
12
13
14
Q7
Q7
9
7
3
4
5
1
C3/
3D
2D
2D
9
6
7
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
74HC_HCT165_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 14 March 2008
2 of 22
NXP Semiconductors
74HC165; 74HCT165
8-bit parallel-in/serial out shift register
11 12 13 14 3
4
5
6
D0 D1 D2 D3 D4 D5 D6 D7
1 PL
10 DS
2 CP
15 CE
8-BIT SHIFT REGISTER
PARALLEL-IN/SERIAL-OUT
Q7 9
Q7 7
mna992
Fig 3.
Functional diagram
6. Pinning information
6.1 Pinning
74HC165
74HCT165
PL
CP
D4
D5
D6
D7
Q7
GND
1
2
3
4
5
6
7
8
001aah564
74HC165
74HCT165
16 V
CC
15 CE
CP
14 D3
13 D2
12 D1
11 D0
10 DS
9
Q7
D4
D5
D6
D7
Q7
2
3
4
5
6
7
8
GND
Q7
9
GND
(1)
terminal 1
index area
16 V
CC
15 CE
14 D3
13 D2
12 D1
11 D0
10 DS
PL
1
001aah565
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
supply pin or input.
Fig 4.
Pin configuration (DIP16, SO16
and (T)SSOP16)
Fig 5.
Pin configuration (DHVQFN16)
74HC_HCT165_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 14 March 2008
3 of 22
NXP Semiconductors
74HC165; 74HCT165
8-bit parallel-in/serial out shift register
6.2 Pin description
Table 2.
Symbol
PL
CP
Q7
GND
Q7
DS
D0 to D7
CE
V
CC
Pin description
Pin
1
2
7
8
9
10
11, 12, 13, 14, 3, 4, 5, 6
15
16
Description
asynchronous parallel load input (active LOW)
clock input (LOW-to-HIGH edge-triggered)
complementary output from the last stage
ground (0 V)
serial output from the last stage
serial data input
parallel data inputs (also referred to as Dn)
clock enable input (active LOW)
positive supply voltage
7. Functional description
Table 3.
Function table
[1]
Inputs
PL
parallel load
serial shift
L
L
H
H
H
H
hold “do nothing”
H
H
[1]
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
q = state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition;
X = don’t care;
↑
= LOW-to-HIGH clock transition.
Operating modes
Qn registers
CE
X
X
L
L
↑
↑
H
X
CP
X
X
↑
↑
L
L
X
H
DS
X
X
l
h
l
h
X
X
D0 to D7 Q0
L
H
X
X
X
X
X
X
L
H
L
H
L
H
q0
q0
L to L
H to H
q0 to q5
q0 to q5
q0 to q5
q0 to q5
q1 to q6
q1 to q6
Outputs
Q7
H
L
q6
q6
q6
q6
q7
q7
L
H
q6
q6
q6
q6
q7
q7
Q1 to Q6 Q7
74HC_HCT165_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 14 March 2008
4 of 22
NXP Semiconductors
74HC165; 74HCT165
8-bit parallel-in/serial out shift register
CP
CE
DS
PL
D0
D1
D2
D3
D4
D5
D6
D7
Q7
Q7
inhibit
load
serial shift
mna993
Fig 6.
Timing diagram
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V)
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
V
I
<
−0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
−0.5
V or V
O
> V
CC
+ 0.5 V
−0.5
V < V
O
< V
CC
+ 0.5 V
[1]
[1]
Conditions
Min
−0.5
-
-
-
-
−50
−65
Max
+7
±20
±20
±25
50
-
+150
Unit
V
mA
mA
mA
mA
mA
°C
74HC_HCT165_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 14 March 2008
5 of 22
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