Philips Semiconductors
Product specification
16-bit D-type registered transceiver; 3-state
FEATURES
•
In accordance with JEDEC standard no 8-1A
•
CMOS low power consumption
•
Direct interface with TTL levels
•
MULTIBYTE™ flow-through pin-out architecture
•
16-bit transceiver with D-type latch
•
Combines 16245 and 16373 type functions in one chip
•
Back-to-back registers for storage
•
Output drive capability 50
Ω
transmission lines at 85
°C
•
Separate controls for data flow in each direction
•
All data inputs have bus hold
•
3-state non-inverting outputs for bus oriented
applications
•
Current drive
±24
mA at 3.0 V.
DESCRIPTION
The 74ALVCH16543 is a dual octal registered transceiver.
Each section contains two sets of D-type latches for
temporary storage of the data flow in either direction.
FUNCTION TABLE
See note 1.
INPUTS
OUTPUTS
nOE
XX
H
X
L
L
L
L
L
L
L
Note
1. XX = AB for A-to-B direction, BA for B-to-A direction;
H = HIGH voltage level; L = LOW voltage level;
nE
XX
X
H
↑
↑
L
L
L
L
L
nLE
XX
X
X
L
L
↑
↑
L
L
H
nB
n
, nA
n
X
X
h
l
h
l
H
L
X
Z
Z
Z
Z
H
L
H
L
NC
74ALVCH16543
Separate latch enable (nLE
AB
, nLE
BA
) and output enable
(nOE
AB
, nOE
BA
) inputs are provided for each register to
permit independent control in either direction of the data
flow.
The ‘16543’ contains two sections each consisting of two
sets of eight D-type latches with separate inputs and
controls for each set. For data flow from A to B, for
example, the A-to-B enable (nE
AB
, where n equals 1 or 2)
inputs must be LOW in order to enter data from nA
0
to nA
7
,
or take data from nB
0
to nB
7
, as indicated in the function
table. With nE
AB
LOW, a LOW signal on the A-to-B latch
enable (nLE
AB
) input makes the A-to-B latches
transparent; a subsequent LOW-to-HIGH transition of the
nLE
AB
signal stores the A data into the latches. With nE
AB
and nOE
AB
both LOW, the 3-state B output buffers are
active and display the data present at the output of the
A latches. Similarly, the nE
BA
, nLE
BA
and nOE
BA
signals
control the data flow from B-to-A.
Active bus hold circuitry is provided to hold unused or
floating data inputs at a valid logic level.
STATUS
disabled
disabled
disabled and latch
latch and display
transparent
hold
h = HIGH state must be present one set-up time before the LOW-to-HIGH transition of nLE
AB
, nLE
BA
, nE
AB
or nE
BA
;
l = LOW state must be present one set-up time before the LOW-to-HIGH transition of nLE
AB
, nLE
BA
, nE
AB
or nE
BA
;
X = don’t care; NC = no change;
↑
= LOW-to-HIGH level transition;
Z = high-impedance OFF-state.
1999 Nov 23
2
Philips Semiconductors
Product specification
16-bit D-type registered transceiver; 3-state
QUICK REFERENCE DATA
Ground = 0; T
amb
= 25
°C;
t
r
= t
f
= 2.5 ns
SYMBOL
t
PHL
/t
PLH
C
I
C
PD
PARAMETER
propagation delay nA
n
, nB
n
to nB
n
, nA
n
input capacitance
power dissipation capacitance per latch
notes 1 and 2
outputs enabled
outputs disabled
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
+
Σ
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
C
L
= output load capacitance in pF;
f
o
= output frequency in MHz;
V
CC
= supply voltage in Volts;
Σ
(C
L
×
V
CC2
×
f
o
) = sum of outputs.
2. The condition is V
I
= GND to V
CC
.
ORDERING INFORMATION
PACKAGE
OUTSIDE NORTH
AMERICA
74ALVCH16543DGG
PINNING
PIN
1 and 28
2 and 27
3 and 26
4, 11, 18, 25, 32, 39, 46 and 53
5, 6, 8, 9, 10, 12, 13 and 14
7, 22, 35 and 50
15, 16, 17, 19, 20, 21, 23 and 24
29 and 56
30 and 55
31 and 54
33, 34, 36, 37, 38, 40, 41 and 42
43, 44, 45, 47, 48, 49, 51 and 52
SYMBOL
1OE
AB
, 2OE
AB
1LE
AB
, 2LE
AB
1E
AB
, 2E
AB
GND
1A
0
to 1A
7
V
CC
2A
0
to 2A
7
2OE
BA
, 1OE
BA
2LE
BA
, 1LE
AB
2E
BA
, 1E
BA
2B
7
to 2B
0
1B
7
to 1B
0
NORTH
AMERICA
ACH16543 DGG
TEMPERATURE
RANGE
−40
to +85
°C
PINS
56
PACKAGE
TSSOP
44
14
CONDITIONS
C
L
= 50 pF;
V
CC
= 3.3 V
3.8
4.0
74ALVCH16543
TYPICAL
ns
pF
pF
pF
UNIT
MATERIAL
plastic
CODE
SOT364-1
DESCRIPTION
output enable A-to-B for register 1 or 2
latch enable A-to-B for register 1 or 2
A-to-B enable for register 1 or 2
ground (0 V)
data inputs/outputs
DC supply voltage
data inputs/outputs
output enable B-to-A for register 1 or 2
latch enable B-to-A for register 1 or 2
B-to-A enable for register 1 or 2
data inputs/outputs
data inputs/outputs
1999 Nov 23
3
测试/测量
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