Si2456/33/14
V. 9 0 , V. 3 4 , V. 3 2
B I S
I SO
M O D E M ®
C
H I PS E T
Features
Data modem formats
ITU-T, Bell
300 bps up to 56 kbps
V.42, V.42bis, MNP2-5
Automatic rate negotiation
WITH
I
N T E G R A T E D
G
L O B A L
DAA
Integrated DAA
Over 5000 V capacitive isolation
Parallel phone detect
Globally-compliant line interface
Overcurrent detection
Caller ID decode
3.3 V power
No external ROM or RAM required
UART with flow control
AT command set support
Fast connect
Parallel interface
Call progress support
Firmware upgradeable
Ordering Information
This data sheet is valid only for
those chipset combinations listed
on page 69.
Applications
Set-top boxes
E-mail terminals
Point-of-sale terminals
Digital video recorders
Security systems
Remote monitoring
Pin Assignments
Description
The Si2456 is a complete, ITU-V.90-compliant, 56 kbps modem chipset
with integrated direct access arrangement (DAA) that provides a
programmable line interface to meet global telephone line requirements
with a single design. Available in two small packages, it eliminates the
need for a separate DSP data pump, external RAM and ROM, modem
controller, codec, isolation transformer, relays, opto-isolators, and 2- to 4-
wire hybrid. The ISOmodem
®
chipset is ideal for embedded modem
applications due to its small board space, low power consumption, and
global compliance. The Si2433 and Si2414 products offer all the same
features as the Si2456 with connect rates of up to 33.6 kbps and
14.4 kbps, respectively.
CLKIN/XTALI
XTALO
CLKOUT/EECS/A0
D6
VD3.3
GND
VDA
RTS/D7
RXD/RD
TXD/WR
CTS/CS
RESET
Si2456/33/14
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
EECLK/D5
DCD/D4
ESC/D3
C1A
ISOB
VD3.3
GND
VDB
EESD/D2
RI/D1
INT/D0
AOUT/INT
Functional Block Diagram
Si3015
QE2
DCT
IGND
C1B
RAM/ROM
Data Bus
Serial
Interface
DAA
Interface
Si3015
C1A
Microcontroller
DSP
1
2
3
4
5
6
7
8
CLKIN/XTALI
CLKOUT
RXD
TXD
CTS
RTS
DCD
ESC
RI
INT
CS
WR
RD
A0
D0-D7
RESET
PLL
Clocking
XTALO
16
15
14
13
12
11
10
9
FILT2
FILT
RX
REXT
REXT2
REF
VREG2
VREG
RNG1
RNG2
QB
QE
To Phone
Line
AOUT
Parallel
Interface
ISOB
Patents pending
Rev. 1.2 8/06
Copyright © 2006 by Silicon Laboratories
Si2456/33/14
Si2456/33/14
T
A B L E
Section
OF
C
O N T E N TS
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3. Bill of Materials: Si2456/33/14 Chipset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1. Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2. Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3. Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.4. Command Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.5. Data Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.6. Fast Connect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.7. V.29 Fast Connect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.8. Clocking/Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.9. Data Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.10. Error Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.11. Wire Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.12. Caller ID Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.13. Parallel Phone Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.14. Overcurrent Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.15. Global Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.16. Firmware Upgrades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.17. EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.18. AT Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.19. Extended AT Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5. S-Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6. User-Access Registers (U-Registers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.1. Bit-Mapped U-Register Detail (defaults in bold) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7. Parallel Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
8. Pin Descriptions: Si2456/33/14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
9. Pin Descriptions: Si3015 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
10. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
11. Package Outline: 24-Pin TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
12. Package Outline: 16-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Rev. 1.2
3
Si2456/33/14
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
1
Ambient Temperature
Ambient Temperature
Si2456/33/14 Supply Voltage, Digital
3
Symbol
T
A
T
A
V
D
Test Condition
K-Grade, F-Grade
B-Grade
Min
2
0
–40
3.0
Typ
25
25
3.3
Max
2
70
85
3.6
Unit
°C
°C
V
Notes:
1.
The Si2456/33/14 specifications are guaranteed when the typical application circuit (including component tolerance)
and any Si2456/33/14 and any Si3015 are used. See "Typical Application Schematic" on page 11.
2.
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated.
3.
The digital supply, V
D
, operates from 3.0 to 3.6 V. The Si2456/33/14 interface supports 5 V logic (CLKIN/XTALI
supports 3.3 V logic only).
4
Rev. 1.2
Si2456/33/14
Table 2. DAA Loop Characteristics
(V
D
= 3.0 to 3.6 V, T
A
= 0 to 70 °C for K-Grade
)
Parameter
DC Termination Voltage
DC Termination Voltage
DC Termination Voltage
DC Termination Voltage
DC Termination Voltage
DC Termination Voltage
DC Termination Voltage
DC Termination Voltage
On-Hook Leakage Current
Operating Loop Current
Operating Loop Current
DC Ring Current
2
Ring Detect Voltage
3
Ring Detect Voltage
3
Ring Frequency
Ringer Equivalence Number
4
Symbol
V
TR
V
TR
V
TR
V
TR
V
TR
V
TR
V
TR
V
TR
I
LK
I
LP
I
LP
Test Condition
I
L
= 20 mA, ACT
1
= 1
DCT = 11 (CTR21)
I
L
= 42 mA, ACT = 1
DCT = 11 (CTR21)
I
L
= 50 mA, ACT = 1
DCT = 11 (CTR21)
I
L
= 60 mA, ACT = 1
DCT = 11 (CTR21)
I
L
= 20 mA, ACT = 0
DCT = 01 (Japan)
I
L
= 100 mA, ACT = 0
DCT = 01 (Japan)
I
L
= 20 mA, ACT = 0
DCT = 10 (FCC)
I
L
= 100 mA, ACT = 0
DCT = 10 (FCC)
V
TR
= –48 V
FCC/Japan Modes
CTR21
DC flowing through
ring detection circuitry
Min
—
—
—
40
—
9
—
9
—
13
13
—
11
17
15
—
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
7.5
14.5
40
—
6.0
—
7.5
—
7
120
60
7
22
33
68
0.2
Unit
V
V
V
V
V
V
V
V
μA
mA
mA
µA
V
rms
V
rms
Hz
V
RD
V
RD
F
R
REN
RT = 0
RT = 1
Notes:
1.
ACT = U67, bit 5; DCT = U67, bits 3:2; RT = U67, bit 0; RZ = U67, bit 1.
2.
R25 and R26 installed.
3.
The ring signal is guaranteed to not be detected below the minimum. The ring signal is guaranteed to be detected
above the maximum.
4.
C15, R14, Z2, and Z3 not installed. RZ = 0.
Rev. 1.2
5
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