PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD72873
IEEE1394 OHCI 1.1 COMPLIANT 2PORT PHY-LINK 1-CHIP HOST CONTROLLER
The
µ
PD72873 is the LSI that integrated OHCI-Link and PHY function into a single chip. The
µ
PD72873 complies
with the 1394 OHCI Specification 1.1 and the IEEE Std 1394a-2000 specifications, and works up to 400 Mbps.
It makes design so compact for PC and PC card application.
FEATURES
• Compliant with Link Layer Services as defined in 1394 Open Host Controller Interface specification release 1.1
• Compliant with Physical Layer Services as defined in IEEE Std 1394a-2000
• Provides two cable ports at 100/200/400 Mbps
• Super Low power consumption for Physical Layer
• Compliant with protocol enhancement as defined in IEEE Std1394a-2000
• Modular 32-bit host interface compliant to PCI Specification release 2.2
• Supports PCI-Bus Power Management Interface Specification release 1.1
• Modular 32-bit host interface compliant to Card Bus Specification
• Cycle Master and Isochronous Resource Manager capable
•
Built-in FIFOs for isochronous transmit (2048 bytes), asynchronous transmit (2048 bytes), and receive (3072
bytes)
• Supports D0, D1, D2, D3hot
• Supports wake up function from D3cold
• 32-bit CRC generation and checking for receive/transmit packets
• 4 isochronous transmit DMAs and 4 isochronous receive DMAs supported
• 32-bit DMA channels for physical memory read/write
• Clock generation by 24.576 MHz X’tal
• 2-wire Serial EEPROM
TM
interface supported
• Separate power supply Link and PHY
• Programmable latency timer from serial EEPROM in Cardbus mode (CARD_ON = 1)
ORDERING INFORMATION
Part number
Package
120-pin plastic TQFP (Fine pitch) (14 x 14)
µ
PD72873GC-YEB
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S15305EJ2V0DS00 (2nd edition)
Date Published April 2002 NS CP (K)
Printed in Japan
The mark
shows major revised points.
2001
µ
PD72873
PIN NAME
AD0 to AD31 : PCI Multiplexed Address and Data
CARD_ON : PCI/Card Select
CBE0 to
CBE3
CLKRUN
CPS
D3CSUP
DEVSEL
FRAME
GND
GNT
: PCICLK Running
: Cable Power Status Input
: D3cold Support
: Device Select
: Cycle Frame
: GND
: Bus_master Grant
: Command/Byte Enables
PERR
PME
PRST
P_AV
DD
P_DV
DD
P_RESET
REQ
RI0
RI1
RSMRST
SERR
STOP
TpA0n
TpA0p
TpA1n
TpA1p
TpB0n
TpB0p
TpB1n
TpB1p
TpBias0
TpBias1
TRDY
XI
XO
: Parity Error
: PME Output
: Reset
: PHY Analog V
DD
: PHY Digital V
DD
: PHY Power on Reset Input
: Bus_master Request
: Resistor0 for Reference Current Setting
: Resistor1 for Reference Current Setting
: Resume Reset
: System Error
: PCI Stop
: Port-1 Twisted Pair A Negative Input/Output
: Port-1 Twisted Pair A Positive Input/Output
: Port-2 Twisted Pair A Negative Input/Output
: Port-2 Twisted Pair A Positive Input/Output
: Port-1 Twisted Pair B Negative Input/Output
: Port-1 Twisted Pair B Positive Input/Output
: Port-2 Twisted Pair B Negative Input/Output
: Port-2 Twisted Pair B Positive Input/Output
: Port-1 Twisted Pair Bias Voltage Output
: Port-2 Twisted Pair Bias Voltage Output
: Target Ready
: X’tal XI
: X’tal XO
GROM_EN : Serial EEPROM Enable
GROM_SCL : Serial EEPROM Clock Output
GROM_SDA : Serial EEPROM Data Input / Output
IC(H)
IC(L)
IC(N)
IDSEL
INTA
IRDY
L_V
DD
PAR
PC0 to PC2
PCI_V
DD
PCLK
: Internally Connected (High Clamped)
: Internally Connected (Low Clamped)
: Internally Connected (Open)
: ID Select
: Interrupt
: Initiator Ready
: V
DD
for Link Digital Core and Link I/Os
: Parity
: Power Class Input
: V
DD
for PCI I/Os
: PCI Clock
Preliminary Data Sheet S15305EJ2V0DS
5
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