Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
V
OUT
T
A
t
r
, t
f
DC Supply Voltage
DC Input Voltage
DC Output Voltage
Operating Temperature Range
Input Rise and Fall Time
V
CC
= 5.0 V
±
0.5 V
Characteristics
Min
3.0
0.0
0.0
−55
0
Max
5.5
5.5
V
CC
+125
20
Unit
V
V
V
°C
ns/V
Device Junction Temperature versus
Time to 0.1% Bond Failures
NORMALIZED FAILURE RATE
Junction
Temperature
°C
80
90
100
110
120
130
140
Time, Hours
1,032,200
419,300
178,700
79,600
37,000
17,800
8,900
Time, Years
117.8
47.9
20.4
9.4
4.2
2.0
1.0
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
TJ = 130
°
C
TJ = 100
°
C
TJ = 120
°
C
TJ = 110
°
C
TJ = 80
°
C
100
TIME, YEARS
TJ = 90
°
C
1
1
10
1000
Figure 3. Failure Rate vs. Time Junction Temperature
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2
NL17SHT126
DC ELECTRICAL CHARACTERISTICS
Symbol
V
IH
Parameter
Minimum High−Level
Input Voltage
Maximum Low−Level
Input Voltage
Minimum High−Level
Output Voltage
V
IN
= V
IH
or V
IL
V
IN
= V
IH
or V
IL
I
OH
=
−
50
mA
V
IN
= V
IH
or V
IL
I
OH
=
−
4 mA
I
OH
=
−
8 mA
V
IN
= V
IH
or V
IL
I
OL
= 50
mA
V
IN
= V
IH
or V
IL
I
OL
= 4 mA
I
OL
= 8 mA
V
IN
= 5.5 V or GND
V
IN
= V
CC
or GND
Input: V
IN
= 3.4 V
Other Input: V
CC
or GND
V
OUT
= 5.5 V
V
IN
= V
IH
or V
IL
V
OUT
= V
CC
or GND
Test Conditions
V
CC
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
3.0
4.5
3.0
4.5
3.0
4.5
0 to
5.5
5.5
5.5
0.0
5.5
2.9
4.4
2.58
3.94
0.0
0.0
0.1
0.1
0.36
0.36
±
0.1
1.0
1.35
0.5
±
0.25
3.0
4.5
T
A
= 25°C
Min
1.4
2.0
2.0
0.53
0.8
0.8
2.9
4.4
2.48
3.80
0.1
0.1
0.44
0.44
±
1.0
20
1.50
5.0
±
2.5
Typ
Max
T
A
≤
85°C
Min
1.4
2.0
2.0
0.53
0.8
0.8
2.9
4.4
2.34
3.66
0.1
0.1
0.52
0.52
±
1.0
40
1.65
10
±
2.5
mA
mA
mA
mA
mA
V
Max
−55
≤
T
A
≤
125°C
Min
1.4
2.0
2.0
0.53
0.8
0.8
Max
Unit
V
V
IL
V
V
OH
V
V
OL
Maximum Low−Level
Output Voltage
V
IN
= V
IH
or V
IL
I
IN
I
CC
I
CCT
I
OPD
I
OZ
Maximum Input Leak-
age Current
Maximum Quiescent
Supply Current
Quiescent Supply
Current
Output Leakage
Current
Maximum 3−State
Leakage Current
AC ELECTRICAL CHARACTERISTICS
Input t
r
= t
f
= 3.0 ns
T
A
= 25°C
Symbol
t
PLH
,
t
PHL
Parameter
Maximum Propagation
Delay, A to Y
(Figures 3 and 5)
Maximum Output
Enable TIme,OE to Y
(Figures 4 and 5)
Maximum Output
Disable Time,OE to Y
(Figures 4 and 5)
Maximum Input
Capacitance
Maximum Three−State
Output Capacitance
(Output in High
Impedance State)
Test Conditions
V
CC
= 3.3
±
0.3 V
V
CC
= 5.0
±
0.5 V
V
CC
= 3.3
±
0.3 V
R
L
= R
I
= 500
W
V
CC
= 5.0
±
0.5 V
R
L
= R
I
= 500
W
V
CC
= 3.3
±
0.3 V
R
L
= R
I
= 500
W
V
CC
= 5.0
±
0.5 V
R
L
= R
I
= 500
W
C
L
= 15pF
C
L
= 50pF
C
L
= 15pF
C
L
= 50pF
C
L
= 15pF
C
L
= 50pF
C
L
= 15pF
C
L
= 50pF
C
L
= 15pF
C
L
= 50pF
C
L
= 15pF
C
L
= 50pF
Min
Typ
5.6
8.1
3.8
5.3
5.4
7.9
3.6
5.1
6.5
8.0
4.8
7.0
4
6
Max
8.0
11.5
5.5
7.5
8.0
11.5
5.1
7.1
9.7
13.2
6.8
8.8
10
T
A
≤
85°C
Min
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Max
9.5
13.0
6.5
8.5
9.5
13.0
6.0
8.0
11.5
15.0
8.0
10.0
10
−55
≤
T
A
≤
125°C
Min
Max
12.0
16.0
8.5
10.5
11.5
15.0
7.5
9.5
14.5
18.0
10.0
12.0
10
pF
pF
ns
ns
Unit
ns
t
PZL
,
t
PZH
t
PLZ
,
t
PHZ
C
in
C
out
Typical @ 25°C, V
CC
= 5.0 V
C
PD
Power Dissipation Capacitance (Note 2)
14
pF
2. C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I
CC(OPR
)
= C
PD
V
CC
f
in
+ I
CC
/ 4 (per buffer). C
PD
is used to determine the
no−load dynamic power consumption; P
D
= C
PD
V
CC2
f
in
+ I
CC
V
CC
.
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3
NL17SHT126
SWITCHING WAVEFORMS
V
CC
50%
GND
t
PZL
Y
50% V
CC
t
PZH
Y
50% V
CC
t
PHZ
t
PLZ
HIGH
IMPEDANCE
V
OL
+ 0.3V
V
OH
- 0.3V
OE
V
CC
50%
A
t
PLH
50% V
CC
Y
t
PHL
GND
Figure 4. Switching Waveforms
Figure 5.
HIGH
IMPEDANCE
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
1 kW
CONNECT TO V
CC
WHEN
TESTING t
PLZ
AND t
PZL.
CONNECT TO GND WHEN
TESTING t
PHZ
AND t
PZH.
C
L
*
DEVICE
UNDER
TEST
C
L
*
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 6. Test Circuit
Figure 7. Test Circuit
INPUT
Figure 8. Input Equivalent Circuit
ORDERING INFORMATION
Device
NL17SHT126P5T5G
Package
SOT−953
(Pb−Free)
Shipping
†
8000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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4
NL17SHT126
PACKAGE DIMENSIONS
SOT−953
CASE 527AE
ISSUE E
D
X
Y
4
E
1
2 3
C
SIDE VIEW
e
5X
A
PIN ONE
INDICATOR
5
H
E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF THE BASE MATERIAL.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS.
DIM
A
b
C
D
E
e
H
E
L
L2
L3
MILLIMETERS
MIN
NOM
MAX
0.34
0.37
0.40
0.10
0.15
0.20
0.07
0.12
0.17
0.95
1.00
1.05
0.75
0.80
0.85
0.35 BSC
0.95
1.00
1.05
0.175 REF
0.05
0.10
0.15
−−−
−−−
0.15
TOP VIEW
L
5X
L3
SOLDERING FOOTPRINT*
0.20
5X
0.35
5X
5X
L2
BOTTOM VIEW
5X
b
0.08 X Y
PACKAGE
OUTLINE
1.20
1
0.35
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor
and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone:
303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax:
303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email:
orderlit@onsemi.com
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800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
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ON Semiconductor Website: www.onsemi.com
Order Literature:
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For additional information, please contact your local
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