MMDF5N02Z
Power MOSFET
5 Amps, 20 Volts
N−Channel SO−8, Dual
EZFETst are an advanced series of Power MOSFETs which con-
tain monolithic back−to−back zener diodes. These zener diodes pro-
vide protection against ESD and unexpected transients. These
miniature surface mount MOSFETs feature low R
DS(on)
and true logic
level performance. They are capable of withstanding high energy in
the avalanche and commutation modes and the drain−to−source diode
has a very low reverse recovery time. EZFET devices are designed for
use in low voltage, high speed switching applications where power ef-
ficiency is important.
•
Zener Protected Gates Provide Electrostatic Discharge Protection
•
Low R
DS(on)
Provides Higher Efficiency and Extends Battery Life
•
Logic Level Gate Drive − Can Be Driven by Logic ICs
•
Miniature SO−8 Surface Mount Package − Saves Board Space
•
Diode Exhibits High Speed, With Soft Recovery
•
I
DSS
Specified at Elevated Temperature
•
Mounting Information for SO−8 Package Provided
MAXIMUM RATINGS
(T
J
= 25°C unless otherwise noted)
Rating
Drain−to−Source Voltage
Drain−to−Gate Voltage (R
GS
= 1.0 MΩ)
Gate−to−Source Voltage − Continuous
Drain Current − Continuous @ T
A
= 25°C
Drain Current
− Continuous @ T
A
= 70°C
Drain Current
− Single Pulse (t
p
≤
10
µs)
Total Power Dissipation @ T
A
= 25°C (Note 1.)
Operating and Storage Temperature Range
Thermal Resistance − Junction to Ambient
Symbol
V
DSS
V
DGR
V
GS
I
D
I
D
I
DM
P
D
T
J
, T
stg
R
θJA
Value
20
20
±
12
5.0
4.5
40
2.0
− 55
to 150
62.5
260
Unit
Vdc
Vdc
Vdc
Adc
Apk
Watts
°C
°C/W
°C
8
1
5N02Z
L
Y
WW
= Device Code
= Location Code
= Year
= Work Week
SO−8, Dual
CASE 751
STYLE 11
5N02Z
LYWW
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5 AMPERES
20 VOLTS
R
DS(on)
= 40 mΩ
N−Channel
D
G
S
MARKING
DIAGRAM
Maximum Temperature for Soldering
T
L
1. When mounted on 1 inch square FR−4 or G−10 board
(V
GS
= 4.5 V, @ 10 Seconds).
PIN ASSIGNMENT
Source−1
Gate−1
Source−2
Gate−2
1
2
3
4
8
7
6
5
Drain−1
Drain−1
Drain−2
Drain−2
Top View
ORDERING INFORMATION
Device
MMDF5N02ZR2
Package
SO−8
Shipping
2500 Tape & Reel
©
Semiconductor Components Industries, LLC, 2004
1
August, 2004 − Rev. XXX
Publication Order Number:
MMDF5N02Z/D
MMDF5N02Z
ELECTRICAL CHARACTERISTICS
(T
A
= 25°C unless otherwise noted)
Characteristic
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
(V
GS
= 0 Vdc, I
D
= 0.25 mAdc)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(V
DS
= 12 Vdc, V
GS
= 0 Vdc)
(V
DS
= 20 Vdc, V
GS
= 0 Vdc)
(V
DS
= 20 Vdc, V
GS
= 0 Vdc, T
J
= 125°C)
Gate−Body Leakage Current (V
GS
=
±
12 Vdc, V
DS
= 0 Vdc)
ON CHARACTERISTICS
(Note 2.)
Gate Threshold Voltage
(V
DS
= V
GS
, I
D
= 0.25 mAdc)
Threshold Temperature Coefficient (Negative)
Static Drain−to−Source On−Resistance
(V
GS
= 4.5 Vdc, I
D
= 5.0 Adc)
(V
GS
= 2.7 Vdc, I
D
= 2.5 Adc)
(Cpk
≥
2.0)
(Note 4.)
V
GS(th)
0.5
−
(Cpk
≥
2.0)
(Note 4.)
R
DS(on)
−
−
g
FS
3.0
34
44
5.6
40
50
−
Mhos
0.78
3.0
1.1
−
Vdc
mV/°C
mΩ
(Cpk
≥
2.0)
(Note 4.)
V
(BR)DSS
20
−
I
DSS
−
−
−
I
GSS
−
−
−
−
−
0.5
15
150
1.5
µAdc
−
15
−
−
Vdc
mV/°C
µAdc
Symbol
Min
Typ
Max
Unit
Forward Transconductance (V
DS
= 9.0 Vdc, I
D
= 2.0 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Transfer Capacitance
SWITCHING CHARACTERISTICS
(Note 3.)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Gate Charge
(V
DS
= 10 Vdc, I
D
= 5.0 Adc,
V
GS
= 4.5 Vdc)
(V
DD
= 6.0 Vdc, I
D
= 5.0 Adc,
V
GS
= 4.5 Vdc, R
G
= 6
Ω)
(V
DS
= 10 Vdc, V
GS
= 0 Vdc,
Vd
Vd
f = 1.0 MHz)
C
iss
C
oss
C
rss
−
−
−
450
330
160
630
460
225
pF
t
d(on)
t
r
t
d(off)
t
f
Q
T
Q
1
Q
2
Q
3
−
−
−
−
−
−
−
−
29
182
190
225
10.7
1.1
5.4
3.5
37
258
238
274
12
−
−
−
ns
nC
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
(I
S
= 5.0 Adc, V
GS
= 0 Vdc)
(I
S
= 5.0 Adc, V
GS
= 0 Vdc,
T
J
= 125°C)
(I
S
= 5.0 Adc, V
GS
= 0 Vdc,
5 0 Ad
Vd
dI
S
/dt = 100 A/µs)
Reverse Recovery Storage Charge
2. Pulse Test: Pulse Width
≤
300
µs,
Duty Cycle
≤
2%.
3. Switching characteristics are independent of operating junction temperature.
4. Reflects typical values.
Max limit − Typ
C
pk
=
3 x SIGMA
V
SD
−
−
t
rr
t
a
t
b
Q
RR
−
−
−
−
0.78
0.65
195
72
123
0.5
1.0
−
−
−
−
−
µC
ns
Vdc
Reverse Recovery Time
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MMDF5N02Z
TYPICAL ELECTRICAL CHARACTERISTICS
10
I D , DRAIN CURRENT (AMPS)
8
7
2.0 V
1.9 V
1.8 V
4
1.7 V
1.6 V
1.5 V
I D , DRAIN CURRENT (AMPS)
6
5
4
3
2
1
0
0
0.4
0.8
1.2
1.6
2
0
0
0.5
1
1.5
100°C
25°C
T
J
= −55°C
2
2.5
8
V
GS
= 12 V
4.5 V
2.7 V
2.3 V
T
J
= 25°C
V
DS
≥
10 V
T
J
= 25°C
6
2
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
Figure 2. Transfer Characteristics
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
2
I
D
= 5 A
T
J
= 25°C
0.08
T
J
= 25°C
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
0
1
2
3
4
5
6
7
8
I
D
, DRAIN CURRENT (AMPS)
V
GS
= 2.7 V
4.5 V
3
4
6
7
5
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
8
Figure 3. On−Resistance versus
Gate−to−Source Voltage
RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
−50
−25
0
25
50
75
100
125
150
V
GS
= 4.5 V
I
D
= 2.5 A
10000
V
GS
= 0 V
1000
I DSS , LEAKAGE (nA)
T
J
= 125°C
100°C
100
10
25°C
1
0.1
0
2.5
5
7.5
10
12.5
15
17.5
20
T
J
, JUNCTION TEMPERATURE (°C)
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation
with Temperature
Figure 6. Drain−to−Source Leakage Current
versus Voltage
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MMDF5N02Z
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge con-
trolled. The lengths of various switching intervals (∆t) are
determined by how fast the FET input capacitance can be
charged by current from the generator.
The published capacitance data is difficult to use for calcu-
lating rise and fall because drain−gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data
is used. In most cases, a satisfactory estimate of average in-
put current (I
G(AV)
) can be made from a rudimentary analy-
sis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a resis-
tive load, V
GS
remains virtually constant at a level known as
the plateau voltage, V
SGP
. Therefore, rise and fall times may
be approximated by the following:
t
r
= Q
2
x R
G
/(V
GG
− V
GSP
)
t
f
= Q
2
x R
G
/V
GSP
where
V
GG
= the gate drive voltage, which varies from zero to V
GG
R
G
= the gate drive resistance
and Q
2
and V
GSP
are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
d(on)
= R
G
C
iss
In [V
GG
/(V
GG
− V
GSP
)]
t
d(off)
= R
G
C
iss
In (V
GG
/V
GSP
)
1400
1200
C, CAPACITANCE (pF)
1000
800
600
400
200
0
−10
−5
0
5
10
15
C
rss
C
iss
C
oss
C
rss
20
C
iss
V
DS
= 0 V
The capacitance (C
iss
) is read from the capacitance curve at
a voltage corresponding to the off−state condition when cal-
culating t
d(on)
and is read at a voltage corresponding to the
on−state when calculating t
d(off)
.
At high switching speeds, parasitic circuit elements com-
plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces
a voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func-
tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal
gate resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea-
sure and, consequently, is not specified.
The resistive switching time variation versus gate resis-
tance (Figure 9) shows how typical switching performance
is affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure
is taken with a resistive load, which approximates an opti-
mally snubbed inductive load. Power MOSFETs may be
safely operated into an inductive load; however, snubbing
reduces switching losses.
V
GS
= 0 V
T
J
= 25°C
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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MMDF5N02Z
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
6
V
DS
5
4
Q3
3
2
1
0
I
D
= 5 A
T
J
= 25°C
0
2
4
6
8
10
12
3
Q1
Q2
2
1
0
14
QT
5
V
GS
4
6
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
1000
V
DD
= 6 V
I
D
= 5 A
V
GS
= 4.5 V
T
J
= 25°C
t, TIME (ns)
t
f
t
d(off)
t
r
100
t
d(on)
10
1
Q
g
, TOTAL GATE CHARGE (nC)
10
R
G
, GATE RESISTANCE (OHMS)
100
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse re-
covery characteristics which play a major role in determin-
ing switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier de-
vice, therefore it has a finite reverse recovery time, t
rr
, due
to the storage of minority carrier charge, Q
RR
, as shown in
the typical reverse recovery wave form of Figure 11. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery fur-
ther increases switching losses. Therefore, one would like a
diode with short t
rr
and low Q
RR
specifications to minimize
these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current ring-
ing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high
5
4.5
4
I S , SOURCE CURRENT (AMPS)
3.5
3
2.5
2
1.5
1
0.5
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
V
GS
= 0 V
T
J
= 25°C
di/dts. The diode’s negative di/dt during t
a
is directly con-
trolled by the device clearing the stored charge. However,
the positive di/dt during t
b
is an uncontrollable diode charac-
teristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of t
b
/t
a
serves
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.
Compared to ON Semiconductor standard cell density
low voltage MOSFETs, high cell density MOSFET diodes
are faster (shorter t
rr
), have less stored charge and a softer re-
verse recovery characteristic. The softness advantage of the
high cell density diode means they can be forced through re-
verse recovery at a higher di/dt than a standard cell MOS-
FET diode without increasing the current ringing or the
noise generated. In addition, power dissipation incurred
from switching the diode will be less due to the shorter re-
covery time and lower switching losses.
V
SD
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
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