Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2 ounce copper trace no air flow.
Tested to EIA/ JESD22−A114−A
Tested to EIA/ JESD22−A115−A
Tested to JESD22−C101−A
Tested to EIA / JESD78.
Table 2. RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
I
V
I/O
T
A
Dt
/
DV
Positive DC Supply Voltage
Control Pin Input Voltage
Switch Input / Output Voltage
Operating Free−Air Temperature
Input Transition Rise or Fall Rate
Control Input
Switch I/O
Parameter
Min
4.0
0
0
−55
0
0
Max
5.5
5.5
5.5
+125
5
DC
Unit
V
V
V
°C
nS/V
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2
NL7SB3257
Table 3. DC ELECTRICAL CHARACTERISTICS
T
A
= 255C
Symbol
V
IK
V
IH
V
IL
I
IN
I
OFF
I
CC
DI
CC
Parameter
Clamp Diode Voltage
High−Level Input Voltage
(Control)
Low−Level Input Voltage
(Control)
Input Leakage Current
Power Off Leakage Current
Quiescent Supply Current
Increase in Supply Current
(Control Pin)
Switch ON Resistance
0
≤
V
IN
≤
5.5 V
V
I/O
= 0 to 5.5 V
I
O
= 0, V
IN
=
V
CC
or 0 V
One input at 3.4
V; Other inputs
at V
CC
or GND
V
I/O
= 0,
I
I/O
= 64 mA
I
I/O
= 30 mA
V
I/O
= 2.4,
I
I/O
= 15 mA
V
I/O
= 2.4,
I
I/O
= 15 mA
Conditions
I
IN
=
−18
mA
V
CC
(V)
4.5
4.0 to 5.5
4.0 to 5.5
5.5
0
5.5
5.5
2.0
0.8
±0.1
±0.1
±0.1
Min
Typ
Max
−1.2
2.0
0.8
±1.0
±1.0
±1.0
2.5
T
A
=
−555C
to +1255C
Min
Max
−1.2
Unit
V
V
V
mA
mA
mA
mA
R
ON
4.5
3
3
6
7
7
15
20
7
7
15
20
W
4.5
4.0
10
Table 4. AC ELECTRICAL CHARACTERISTICS
T
A
= 255C
Symbol
t
PD
Parameter
Propagation Delay,
A to B or B to A
Output Enable Time
V
CC
(V)
4.0 to 5.5
Test Condition
See Figure 4
Min
Typ
Max
0.25
T
A
=
−555C
to +1255C
Min
Max
0.25
Unit
ns
t
EN
4.5 to 5.5
4.0
0.8
0.8
0.8
0.8
V
IN
= 3 V or 0
Switch ON
Switch OFF
2.5
3.0
3.1
2.9
4.2
4.6
4.8
4.4
2.0
10
5.0
0.8
0.8
0.8
0.8
4.2
4.6
4.8
4.4
ns
t
DIS
Output Disable Time
4.5 to 5.5
4.0
ns
C
IN
C
IO(ON)
C
IO(OFF)
Control Input Capacitance
Switch On Capacitance
Switch Off Capacitance
5.0
5.0
5.0
pF
pF
pF
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3
NL7SB3257
AC Loading and Waveforms
7V
From Output
Under Test
C
L
= 50 pF
(see Note A)
500
W
S1
Open
GND
500
W
TEST
t
PD
t
PLZ
/t
PZL
t
PHZ
/t
PZH
S1
Open
7V
GND
LOAD CIRCUIT
Output
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
t
PZL
3V
1.5 V
1.5 V
0V
t
PLZ
3.5 V
1.5 V
t
PZH
1.5 V
V
OL
+ 0.3 V
t
PHZ
V
OH
−
0.3 V
V
OH
0V
V
OL
3V
Input
t
PHL
Output
1.5 V
1.5 V
1.5 V
0V
t
PLH
V
OH
1.5 V
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
A. C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
≤
10 MHz, Z
O
= 50
W,
t
r
≤
2.5 ns, t
f
≤
2.5 ns.
D. The output is measured with one input transition per measurement.
E. t
PLZ
and t
PHZ
are the same as t
dis
.
F. t
PZL
and t
PZH
are the same as t
en
.
G. t
PLH
and t
PHL
are the same as t
pd
.
Figure 3. Load Circuit and Voltage Waveforms
DEVICE ORDERING INFORMATION
Device
NL7SB3257CMX1TCG
Package
ULLGA6
−
1.0 x 1.0, 0.35P
(Pb−Free)
Shipping
†
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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4
NL7SB3257
PACKAGE DIMENSIONS
ULLGA6 1.0x1.0, 0.35P
CASE 613AD
ISSUE A
D
A
B
0.10 C
0.10 C
0.05 C
6X
0.05 C
L1
1
ON Semiconductor
and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer
purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone:
303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax:
303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email:
orderlit@onsemi.com
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800−282−9855 Toll Free
USA/Canada
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Phone: 421 33 790 2910
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Phone: 81−3−5817−1050
ON Semiconductor Website: www.onsemi.com
Order Literature:
http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
ÉÉ
ÉÉ
1
6
PIN ONE
REFERENCE
E
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.30 mm FROM THE TERMINAL TIP.
4. A MAXIMUM OF 0.05 PULL BACK OF THE
PLATED TERMINAL FROM THE EDGE OF THE
PACKAGE IS ALLOWED.
DIM
A
A1
b
D
E
e
L
L1
MILLIMETERS
MIN
MAX
−−−
0.40
0.00
0.05
0.12
0.22
1.00 BSC
1.00 BSC
0.35 BSC
0.25
0.35
0.30
0.40
TOP VIEW
A
SIDE VIEW
A1
e
5X
3
SEATING
PLANE
C
MOUNTING FOOTPRINT
SOLDERMASK DEFINED*
0.48
5X
0.22
6X
L
NOTE 4
1.18
0.53
4
6X
b
0.10 C A B
0.05 C
NOTE 3
PKG
OUTLINE
0.35
PITCH
DIMENSIONS: MILLIMETERS
BOTTOM VIEW
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
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