MMSF3P03HD
Preferred Device
Power MOSFET
3 Amps, 30 Volts
P−Channel SO−8
These miniature surface mount MOSFETs feature ultra low R
DS(on)
and true logic level performance. They are capable of withstanding
high energy in the avalanche and commutation modes and the
drain−to−source diode has a very low reverse recovery time.
MiniMOSt devices are designed for use in low voltage, high speed
switching applications where power efficiency is important. Typical
applications are dc−dc converters, and power management in portable
and battery powered products such as computers, printers, cellular and
cordless phones. They can also be used for low voltage motor controls
in mass storage products such as disk drives and tape drives. The
avalanche energy is specified to eliminate the guesswork in designs
where inductive loads are switched and offer additional safety margin
against unexpected voltage transients.
•
Ultra Low R
DS(on)
Provides Higher Efficiency and Extends Battery
Life
•
Logic Level Gate Drive − Can Be Driven by Logic ICs
•
Miniature SO−8 Surface Mount Package − Saves Board Space
•
Diode Is Characterized for Use In Bridge Circuits
•
Diode Exhibits High Speed, With Soft Recovery
•
I
DSS
Specified at Elevated Temperature
•
Avalanche Energy Specified
•
Mounting Information for SO−8 Package Provided
8
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3 AMPERES
30 VOLTS
R
DS(on)
= 100 mW
P−Channel
D
G
S
MARKING
DIAGRAM
MAXIMUM RATINGS
(T
J
= 25°C unless otherwise noted) (Note 1.)
Rating
Drain−to−Source Voltage
Drain−to−Gate Voltage (R
GS
= 1.0 MΩ)
Gate−to−Source Voltage − Continuous
Drain Current − Continuous @ T
A
= 25°C
Drain Current
− Continuous @ T
A
= 100°C
Drain Current
− Single Pulse (t
p
≤
10
µs)
Total Power Dissipation @ T
A
= 25°C
(Note 2.)
Operating and Storage Temperature Range
Single Pulse Drain−to−Source Avalanche
Energy − Starting T
J
= 25°C
(V
DD
= 20 Vdc, V
GS
= 5.0 Vdc,
I
L
= 9.0 Apk, L = 14 mH, R
G
= 25
Ω)
Thermal Resistance − Junction to Ambient
(Note 2.)
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
Symbol
V
DSS
V
DGR
V
GS
I
D
I
D
I
DM
P
D
Value
30
30
±
20
4.6
3.0
50
2.5
Unit
Vdc
Vdc
Vdc
Adc
Apk
Watts
°C
mJ
SO−8
CASE 751
STYLE 13
1
L
Y
WW
= Location Code
= Year
= Work Week
S3P03
LYWW
PIN ASSIGNMENT
N−C
Source
Source
Gate
1
2
3
4
8
7
6
5
Drain
Drain
Drain
Drain
− 55 to 150
E
AS
567
Top View
R
θJA
T
L
50
260
°C/W
°C
ORDERING INFORMATION
Device
MMSF3P03HDR2
Package
SO−8
Shipping
2500 Tape & Reel
1. Negative sign for P−Channel device omitted for clarity.
2. Mounted on 2″ square FR4 board (1″ sq. 2 oz. Cu 0.06″ thick single sided),
10 sec. max.
Preferred
devices are recommended choices for future use
and best overall value.
©
Semiconductor Components Industries, LLC, 2000
1
September, 2004 − Rev. XXX
Publication Order Number:
MMSF3P03HD/D
MMSF3P03HD
ELECTRICAL CHARACTERISTICS
(T
C
= 25°C unless otherwise noted) (Note 1.)
Characteristic
OFF CHARACTERISTICS
Drain−Source Breakdown Voltage
(V
GS
= 0 Vdc, I
D
= 250
µAdc)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(V
DS
= 30 Vdc, V
GS
= 0 Vdc)
(V
DS
= 30 Vdc, V
GS
= 0 Vdc, T
J
= 125°C)
Gate−Body Leakage Current (V
GS
=
±
20 Vdc, V
DS
= 0)
ON CHARACTERISTICS
(Note 3.)
Gate Threshold Voltage
(V
DS
= V
GS
, I
D
= 250
µAdc)
Temperature Coefficient (Negative)
Static Drain−to−Source On−Resistance
(V
GS
= 10 Vdc, I
D
= 3.0 Adc)
(V
GS
= 4.5 Vdc, I
D
= 1.5 Adc)
Forward Transconductance (V
DS
= 3.0 Vdc, I
D
= 1.5 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Transfer Capacitance
SWITCHING CHARACTERISTICS
(Note 4.)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Gate Charge
(V
DS
= 24 Vdc, I
D
= 3.0 Adc,
V
GS
= 10 Vdc)
(V
DS
= 15 Vdc, I
D
= 3.0 Adc,
V
GS
= 10 Vdc,
Vdc
R
G
= 6.0
Ω)
(V
DS
= 15 Vdc, I
D
= 3.0 Adc,
V
GS
= 4.5 Vdc,
4 5 Vdc
R
G
= 6.0
Ω)
t
d(on)
t
r
t
d(off)
t
f
t
d(on)
t
r
t
d(off)
t
f
Q
T
Q
1
Q
2
Q
3
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage (Note 1.)
(I
S
= 3.0 Adc, V
GS
= 0 Vdc)
(I
S
= 3.0 Adc, V
GS
= 0 Vdc,
T
J
= 125°C)
V
SD
−
−
t
rr
(I
S
= 3.0 Adc,
dI
S
/dt = 100 A/µs)
Reverse Recovery Stored Charge
1. Negative sign for P−Channel device omitted for clarity.
3. Pulse Test: Pulse Width
≤
300
µs,
Duty Cycle
≤
2%.
4. Switching characteristics are independent of operating junction temperature.
t
a
t
b
Q
RR
−
−
−
−
1.3
0.85
31
22
9.0
0.034
2.0
−
−
−
−
−
µC
ns
Vdc
−
−
−
−
−
−
−
−
−
−
−
−
26
102
67
69
14
32
104
66
32.4
2.7
9.0
6.9
52
204
134
138
28
64
208
132
45
−
−
−
nC
ns
(V
DS
= 24 Vdc, V
GS
= 0 Vdc,
Vd
Vd
f = 1.0 MHz)
C
iss
C
oss
C
rss
−
−
−
1015
470
135
1420
660
190
pF
V
GS(th)
1.0
−
R
DS(on)
−
−
g
FS
3.0
0.080
0.090
5.0
0.100
0.110
−
mhos
1.5
3.9
2.0
−
Vdc
mV/°C
Ohm
V
(BR)DSS
30
−
I
DSS
−
−
I
GSS
−
−
−
5.0
1.0
10
100
nAdc
−
30
−
−
Vdc
mV/°C
µAdc
Symbol
Min
Typ
Max
Unit
Reverse Recovery Time
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2
MMSF3P03HD
TYPICAL ELECTRICAL CHARACTERISTICS
6
V
GS
= 10 V
I D , DRAIN CURRENT (AMPS)
5
3.8 V
4
2.9 V
3
2
1
2.4 V
0
0
0.4
0.8
1.2
1.6
2
0
2
2.2
2.4
2.7 V
4.5 V
3.1 V
I D , DRAIN CURRENT (AMPS)
T
J
= 25°C
5
4
3
2
1
− 55°C
2.6
2.8
3
3.2
T
J
= 100°C
25°C
6
V
DS
≥
10 V
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
Figure 2. Transfer Characteristics
0.6
I
D
= 1.5 A
0.5
0.4
0.3
0.2
0.1
0
0
2
4
6
8
10
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
0.095
T
J
= 25°C
0.09
V
GS
= 4.5 V
0.085
0.08
10 V
0.075
0.07
0
1
2
3
4
5
6
I
D
, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus
Gate−To−Source Voltage
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
RDS(on) , DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
3.0
2.5
2.0
1.5
1.0
0.5
0
−50
V
GS
= 4.5 V
I
D
= 1.5 A
1000
V
GS
= 0 V
T
J
= 125°C
I DSS , LEAKAGE (nA)
100
10
100°C
−25
0
25
50
75
100
125 150
1
0
5
10
15
20
25
30
T
J
, JUNCTION TEMPERATURE (°C)
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−To−Source Leakage
Current versus Voltage
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3
MMSF3P03HD
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (∆t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
G(AV)
) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V
GS
remains virtually constant at a level
known as the plateau voltage, V
SGP
. Therefore, rise and fall
times may be approximated by the following:
t
r
= Q
2
x R
G
/(V
GG
− V
GSP
)
t
f
= Q
2
x R
G
/V
GSP
where
V
GG
= the gate drive voltage, which varies from zero to V
GG
R
G
= the gate drive resistance
and Q
2
and V
GSP
are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
d(on)
= R
G
C
iss
In [V
GG
/(V
GG
− V
GSP
)]
t
d(off)
= R
G
C
iss
In (V
GG
/V
GSP
)
3500
V
DS
= 0 V
3000
C
iss
C, CAPACITANCE (pF)
2500
2000
1500
1000
C
oss
500
0
10
5
V
GS
0
V
DS
C
rss
5
10
15
20
25
30
V
GS
= 0 V
The capacitance (C
iss
) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating t
d(on)
and is read at a voltage corresponding to the
on−state when calculating t
d(off)
.
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
T
J
= 25°C
C
rss
C
iss
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (Volts)
Figure 7. Capacitance Variation
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4
MMSF3P03HD
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
12
QT
10
8
6
4 Q1
2
0
Q3
Q2
I
D
= 3 A
T
J
= 25°C
V
DS
V
GS
16
12
8
4
0
35
20
24
1000
V
DD
= 15 V
I
D
= 3 A
V
GS
= 10 V
T
J
= 25°C
t, TIME (ns)
t
d(off)
t
f
t
r
t
d(on)
10
1
10
R
G
, GATE RESISTANCE (OHMS)
100
VDS , DRAIN−TO−SOURCE VOLTAGE (VOLTS)
100
0
5
10
15
20
25
30
Q
T
, TOTAL CHARGE (nC)
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse
recovery characteristics which play a major role in
determining switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier
device, therefore it has a finite reverse recovery time, t
rr
, due
to the storage of minority carrier charge, Q
RR
, as shown in
the typical reverse recovery wave form of Figure 15. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery
further increases switching losses. Therefore, one would
like a diode with short t
rr
and low Q
RR
specifications to
minimize these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current
ringing. The mechanisms at work are finite irremovable
circuit parasitic inductances and capacitances acted upon by
high di/dts. The diode’s negative di/dt during t
a
is directly
controlled by the device clearing the stored charge.
However, the positive di/dt during t
b
is an uncontrollable
diode characteristic and is usually the culprit that induces
current ringing. Therefore, when comparing diodes, the
ratio of t
b
/t
a
serves as a good indicator of recovery
abruptness and thus gives a comparative estimate of
probable noise generated. A ratio of 1 is considered ideal and
values less than 0.5 are considered snappy.
Compared to ON Semiconductor standard cell density
low voltage MOSFETs, high cell density MOSFET diodes
are faster (shorter t
rr
), have less stored charge and a softer
reverse recovery characteristic. The softness advantage of
the high cell density diode means they can be forced through
reverse recovery at a higher di/dt than a standard cell
MOSFET diode without increasing the current ringing or the
noise generated. In addition, power dissipation incurred
from switching the diode will be less due to the shorter
recovery time and lower switching losses.
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