MMDF7N02Z
Power MOSFET
7 Amps, 20 Volts
N−Channel SO−8, Dual
EZFETst are an advanced series of Power MOSFETs which
contain monolithic back−to−back zener diodes. These zener diodes
provide protection against ESD and unexpected transients. These
miniature surface mount MOSFETs feature ultra low R
DS(on)
and true
logic level performance. They are capable of withstanding high energy
in the avalanche and commutation modes and the drain−to−source
diode has a very low reverse recovery time. EZFET devices are
designed for use in low voltage, high speed switching applications
where power efficiency is important. Typical applications are dc−dc
converters, and power management in portable and battery powered
products such as computers, printers, cellular and cordless phones.
They can also be used for low voltage motor controls in mass storage
products such as disk drives and tape drives.
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7 AMPERES
20 VOLTS
R
DS(on)
= 27 mΩ
N−Channel
D
•
Zener Protected Gates Provide Electrostatic Discharge Protection
•
Designed to Withstand 200 V Machine Model and 2000 V Human
•
•
•
•
•
•
•
Body Model
Ultra Low R
DS(on)
Provides Higher Efficiency and Extends Battery
Life
Logic Level Gate Drive − Can be Driven by Logic ICs
Miniature SO−8 Surface Mount Package − Saves Board Space
Diode is Characterized for use in Bridge Circuits
Diode Exhibits High Speed, with Soft Recovery
I
DSS
Specified at Elevated Temperature
Mounting Information for SO−8 Package Provided
G
S
MARKING
DIAGRAM
8
1
7N02Z
L
Y
WW
SO−8, Dual
CASE 751
STYLE 11
7N02Z
LYWW
= Device Code
= Location Code
= Year
= Work Week
PIN ASSIGNMENT
Source−1
Gate−1
Source−2
Gate−2
1
2
3
4
8
7
6
5
Drain−1
Drain−1
Drain−2
Drain−2
Top View
ORDERING INFORMATION
Device
MMDF7N02ZR2
Package
SO−8
Shipping
2500 Tape & Reel
©
Semiconductor Components Industries, LLC, 2001
1
September, 2004 − Rev. XXX
Publication Order Number:
MMDF7N02Z/D
MMDF7N02Z
MAXIMUM RATINGS
(T
J
= 25°C unless otherwise noted)
Rating
Drain−to−Source Voltage
Drain−to−Gate Voltage (R
GS
= 1.0 MΩ)
Gate−to−Source Voltage − Continuous
Drain Current
Continuous @ T
A
= 25°C (Note 1.)
Continuous @ T
A
= 70°C (Note 1.)
Pulsed Drain Current (Note 3.
)
Total Power Dissipation @ T
A
= 25°C (Note 1.)
Linear Derating Factor @ T
A
= 25°C (Note 1.)
Total Power Dissipation @ T
A
= 25°C (Note 2.)
Linear Derating Factor @ T
A
= 25°C (Note 2.)
Operating and Storage Temperature Range
Symbol
V
DSS
V
DGR
V
GS
I
D
I
D
I
DM
P
D
P
D
T
J
, T
stg
Max
20
20
±12
7.0
4.6
35
2.0
16
1.39
11.11
− 55 to 150
Watts
mW/°C
Watts
mW/°C
°C
Unit
Vdc
Vdc
Vdc
Adc
THERMAL RESISTANCE
Parameter
Junction−to−Ambient (Note 1.)
Junction−to−Ambient (Note 2.)
Symbol
R
qJA
Typ
−
−
Max
62.5
90
Unit
°C/W
ELECTRICAL CHARACTERISTICS
(T
C
= 25°C unless otherwise noted)
Characteristic
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
(V
GS
= 0 Vdc, I
D
= 0.25 mAdc)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(V
DS
= 20 Vdc, V
GS
= 0 Vdc)
(V
DS
= 20 Vdc, V
GS
= 0 Vdc, T
J
= 125°C)
Gate−Body Leakage Current (V
GS
=
±12
Vdc, V
DS
= 0 Vdc)
ON CHARACTERISTICS
(Note 4.)
Gate Threshold Voltage
(Cpk
≥
2.0) (Notes 4. & 5.)
(V
DS
= V
GS
, I
D
= 0.25 mAdc)
Threshold Temperature Coefficient (Negative)
Static Drain−to−Source On−Resistance
(V
GS
= 4.5 Vdc, I
D
= 7.0 Adc)
(V
GS
= 2.5 Vdc, I
D
= 3.5 Adc)
(Cpk
≥
2.0) (Notes 4. & 5.)
V
GS(th)
0.5
−
R
DS(on)
−
−
g
FS
5.0
23
30
11
27
35
−
Mhos
0.7
2.5
1.0
−
Vdc
mV/°C
mΩ
(Cpk
≥
2.0) (Notes 4. & 5.)
V
(BR)DSS
20
−
I
DSS
−
−
I
GSS
−
−
−
−
1.0
10
3.0
µAdc
−
15
−
−
Vdc
mV/°C
µAdc
Symbol
Min
Typ
Max
Unit
Forward Transconductance (V
DS
= 10 Vdc, I
D
= 6.0 Adc) (Note 4.)
1.
2.
3.
4.
5.
When mounted on 1″ square FR4 or G−10 board (V
GS
= 10 V, @ 10 seconds).
When mounted on minimum recommended FR4 or G−10 board (V
GS
= 10 V, @ Steady State).
Repetitive rating; pulse width limited by maximum junction temperature.
Pulse Test: Pulse Width
≤
300
µs,
Duty Cycle
≤
2%.
Reflects typical values.
Max limit − Typ
C
pk
=
3 x SIGMA
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2
MMDF7N02Z
ELECTRICAL CHARACTERISTICS
(T
C
= 25°C unless otherwise noted)
Characteristic
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Transfer Capacitance
SWITCHING CHARACTERISTICS
(Note 7.)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Gate Charge
See Figure 8
S Fi
(V
DS
= 12 Vdc, I
D
= 5.0 Adc,
V
GS
= 4.5 Vdc) (Note 6.)
(V
DD
= 10 Vdc, I
D
= 1.0 Adc,
V
GS
= 4.5 Vdc,
4 5 Vdc
R
G
= 6.0
Ω)
(Note 6.)
t
d(on)
t
r
t
d(off)
t
f
Q
T
Q
1
Q
2
Q
3
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
Reverse Recovery Time
(I
S
= 7.0 Adc, V
GS
= 0 Vdc,
dI
S
/dt = 100 A/µs) (Note 6.)
Reverse Recovery Stored Charge
6. Pulse Test: Pulse Width
≤
300
µs,
Duty Cycle
≤
2%.
7. Switching characteristics are independent of operating junction temperatures.
(I
S
= 7.0 Adc, V
GS
= 0 Vdc) (Note 6.)
(I
S
= 7.0 Adc, V
GS
= 0 Vdc, T
J
= 125°C)
V
SD
t
rr
t
a
t
b
Q
RR
−
−
−
−
−
−
0.90
0.84
780
190
590
5.7
1.1
−
−
−
−
−
µC
Vdc
ns
−
−
−
−
−
−
−
−
31
230
725
780
17
1.4
6.7
6.5
62
460
1450
1560
24
−
−
−
nC
ns
(V
DS
= 16 Vdc, V
GS
= 0 Vdc,
Vd
Vd
f = 1.0 MHz)
C
iss
C
oss
C
rss
−
−
−
450
350
110
630
490
155
pF
Symbol
Min
Typ
Max
Unit
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MMDF7N02Z
TYPICAL ELECTRICAL CHARACTERISTICS
15
ID, DRAIN CURRENT (AMPS)
10 V
12
4.5 V
1.9 V
9.0
V
GS
= 1.7 V
6.0
ID, DRAIN CURRENT (AMPS)
2.3 V
2.1 V
15
T
J
= 25_C
V
DS
≥
10 V
12
9.0
25_C
6.0
T
J
= 100_C
3.0
0
0
−55_C
3.0
0
0
0.5
1.0
1.5
2.0
0.5
1.0
1.5
2.0
2.5
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.06
I
D
= 7.0 A
T
J
= 25_C
0.05
T
J
= 25_C
0.04
V
GS
= 2.7 V
4.5 V
0.02
0.05
0.04
0.03
0.03
0.02
0.01
0
4.0
6.0
8.0
2.0
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
10
0.01
0
0
2.0
4.0
6.0
8.0
I
D
, DRAIN CURRENT (AMPS)
10
12
Figure 3. On−Resistance versus
Drain Current
RDS(on) , DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
2.0
V
GS
= 4.5 V
I
D
= 3.5 A
10,000
V
GS
= 0 V
I DSS , LEAKAGE (nA)
1000
T
J
= 125_C
100_C
1.5
100
1.0
10
25_C
1.0
0.5
0
−50
−25
0
25
50
75
100
125
150
T
J
, JUNCTION TEMPERATURE (_C)
0.1
0
4.0
8.0
12
16
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
20
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−To−Source Leakage
Current versus Voltage
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MMDF7N02Z
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (∆t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
G(AV)
) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V
GS
remains virtually constant at a level
known as the plateau voltage, V
SGP
. Therefore, rise and fall
times may be approximated by the following:
t
r
= Q
2
x R
G
/(V
GG
− V
GSP
)
t
f
= Q
2
x R
G
/V
GSP
where
V
GG
= the gate drive voltage, which varies from zero to V
GG
R
G
= the gate drive resistance
and Q
2
and V
GSP
are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
d(on)
= R
G
C
iss
In [V
GG
/(V
GG
− V
GSP
)]
t
d(off)
= R
G
C
iss
In (V
GG
/V
GSP
)
3000
V
DS
= 0 V
C, CAPACITANCE (pF)
2500
C
iss
2000
1500
1000
C
rss
500
0
−10
V
GS
= 0 V
T
J
= 25_C
The capacitance (C
iss
) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating t
d(on)
and is read at a voltage corresponding to the
on−state when calculating t
d(off)
.
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
C
iss
C
oss
C
rss
C
oss
−5.0
0
5.0
10
15
20
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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