MMDF3N06HD
Preferred Device
Advance Information
Power MOSFET
3 Amps, 60 Volts
N−Channel SO−8, Dual
These miniature surface mount MOSFETs feature low R
DS(on)
and
true logic level performance. Dual MOSFET devices are designed for
use in low voltage, high speed switching applications where power
efficiency is important. Typical applications are dc−dc converters, and
power management in portable and battery powered products such as
computers, printers, cellular and cordless phones. They can also be
used for low voltage motor controls in mass storage products such as
disk drives and tape drives.
•
Low R
DS(on)
Provides Higher Efficiency and Extends Battery Life
•
Logic Level Gate Drive − Can Be Driven by Logic ICs
•
Miniature SO−8 Surface Mount Package − Saves Board Space
•
Diode Is Characterized for Use In Bridge Circuits
•
Diode Exhibits High Speed, With Soft Recovery
•
I
DSS
Specified at Elevated Temperature
•
Mounting Information for SO−8 Package Provided
MAXIMUM RATINGS
(T
J
= 25°C unless otherwise noted)
Rating
Drain−to−Source Voltage
Gate−to−Source Voltage − Continuous
Drain Current − Continuous @ T
A
= 25°C
Source Current − Continuous @ T
A
= 25°C
Total Power Dissipation @ T
A
= 25°C
(Note 1.)
Operating and Storage Temperature Range
Single Pulse Drain−to−Source Avalanche
Energy − Starting T
J
= 25°C
(V
DD
= 60 Vdc, V
GS
= 5.0 Vdc,
V
DS
= 32 Vdc, I
L
= 15 Apk, L = 10 mH,
R
G
= 25
Ω)
Thermal Resistance − Junction−to−Ambient
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
Symbol
V
DSS
V
GS
I
D
I
DM
I
S
P
D
T
J
, T
stg
E
AS
Value
60
±
20
3.3
16.5
1.7
2.0
− 55 to
150
105
Unit
Vdc
Vdc
Adc
Apk
Adc
Watts
°C
mJ
L
Y
WW
= Location Code
= Year
= Work Week
8
1
SO−8, Dual
CASE 751
STYLE 11
D3N06
LYWW
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3 AMPERES
60 VOLTS
R
DS(on)
= 100 mW
N−Channel
D
D
G
S
G
S
MARKING
DIAGRAM
PIN ASSIGNMENT
Source−1
R
θJA
T
L
62.5
260
°C/W
°C
Gate−1
Source−2
Gate−2
1
2
3
4
8
7
6
5
Drain−1
Drain−1
Drain−2
Drain−2
1. Mounted on G10/FR4 glass epoxy board using minimum recommended
footprint.
Top View
ORDERING INFORMATION
Device
MMDF3N06HDR2
Package
SO−8
Shipping
2500 Tape & Reel
This document contains information on a new product. Specifications and information
herein are subject to change without notice.
Preferred
devices are recommended choices for future use
and best overall value.
©
Semiconductor Components Industries, LLC, 2000
1
September, 2004 − Rev. XXX
Publication Order Number:
MMDF3N06HD/D
MMDF3N06HD
ELECTRICAL CHARACTERISTICS
(T
A
= 25°C unless otherwise noted)
Characteristic
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
(V
GS
= 0 Vdc, I
D
= 0.25 mAdc)
Zero Gate Voltage Drain Current
(V
DS
= 48 Vdc, V
GS
= 0 Vdc)
(V
DS
= 48 Vdc, V
GS
= 0 Vdc, T
J
= 125°C)
Gate−Body Leakage Current (V
GS
=
±
20 Vdc, V
DS
= 0 Vdc)
ON CHARACTERISTICS
(Note 2.)
Gate Threshold Voltage
(V
DS
= V
GS
, I
D
= 0.25 mAdc)
Static Drain−to−Source On−Resistance
(V
GS
= 10 Vdc, I
D
= 3.3 Adc)
(V
GS
= 4.5 Vdc, I
D
= 2.5 Adc)
Forward Transconductance
(V
DS
= 15 Vdc, I
D
= 1.5 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Transfer Capacitance
SWITCHING CHARACTERISTICS
(Note 3.)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Gate Charge
(See Figure 8)
(S Fi
(V
DS
= 30 Vdc, I
D
= 3.3 Adc,
V
GS
= 10 Vdc)
(V
DD
= 15 Vdc, I
D
= 3.0 Adc,
V
GS
= 10 Vdc,
Vdc
R
G
= 9.1
Ω)
(V
DD
= 30 Vdc, I
D
= 3.3 Adc,
V
GS
= 4.5 Vdc,
4 5 Vdc
R
G
= 30
Ω)
t
d(on)
t
r
t
d(off)
t
f
t
d(on)
t
r
t
d(off)
t
f
Q
T
Q
1
Q
2
Q
3
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
(I
S
= 1.7 Adc, V
GS
= 0 Vdc)
(I
S
= 1.7 Adc, V
GS
= 0 Vdc, T
J
= 125°C)
Reverse Recovery Time
(I
S
= 1.7 Adc, V
GS
= 0 Vdc,
1 7 Ad
Vd
dI
S
/dt = 100 A/µs)
Reverse Recovery Stored Charge
2. Pulse Test: Pulse Width
≤
300
µs,
Duty Cycle
≤
2%.
3. Switching characteristics are independent of operating junction temperature.
t
rr
t
a
t
b
Q
RR
V
SD
−
−
−
−
−
−
0.78
0.65
27.9
23
4.9
0.038
1.2
−
−
−
−
−
µC
ns
Vdc
−
−
−
−
−
−
−
−
−
−
−
−
10.6
15.9
23.8
14.7
7.0
4.8
32.4
14.2
14.5
1.8
3.5
3.75
22.1
31.8
47.6
29.4
14
9.6
64.8
28.4
29
−
−
−
nC
ns
ns
(V
DS
= 25 Vdc, V
GS
= 0 Vdc,
Vd
Vd
f = 1.0 MHz)
C
iss
C
oss
C
rss
−
−
−
442
97.6
24.4
618
137
34.2
pF
V
GS(th)
1.0
R
DS(on)
−
−
g
FS
−
7.5
−
67.5
82.5
100
200
Mhos
−
−
mW
Vdc
V
(BR)DSS
60
I
DSS
−
−
I
GSS
−
0.001
0.05
12
1.0
25
100
nAdc
−
−
µAdc
Vdc
Symbol
Min
Typ
Max
Unit
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2
MMDF3N06HD
TYPICAL ELECTRICAL CHARACTERISTICS
6.0
I D , DRAIN CURRENT (AMPS)
5.0
6.0
3.3 V
3.5 V
3.7 V
3.9 V
3.1 V
I D , DRAIN CURRENT (AMPS)
T
J
= 25°C
2.9 V
5.0
4.0
3.0
2.0
1.0
0
1.6
1.8
2.0
1.5
1.75
2.0
2.25
2.5
2.75
3.0
3.25
3.5
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
100°C
25°C
T
J
= −55°C
V
DS
≥
10 V
V
GS
= 10 V
6.0 V
4.5 V
4.3 V
4.0
4.1 V
3.0
2.0
2.7 V
2.5 V
1.0
0
2.3 V
2.1 V
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
Figure 2. Transfer Characteristics
0.3
0.25
0.2
0.15
0.1
0.05
0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
10
I
D
= 3.0 A
T
J
= 25°C
0.09
T
J
= 25°C
0.085
0.08
0.075
0.07
10 V
0.065
0.06
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
I
D
, DRAIN CURRENT (AMPS)
V
GS
= 4.5 V
Figure 3. On−Resistance versus
Gate−to−Source Voltage
RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
−50
I DSS , LEAKAGE (nA)
V
GS
= 10 V
I
D
= 1.5 A
1000
V
GS
= 0 V
100
T
J
= 125°C
10
100°C
1.0
25°C
0
−25
0
25
50
75
100
125
150
0
5.0
10
15
20
25
30
T
J
, JUNCTION TEMPERATURE (°C)
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation
with Temperature
Figure 6. Drain−to−Source Leakage Current
versus Voltage
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3
MMDF3N06HD
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (∆t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
G(AV)
) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V
GS
remains virtually constant at a level
known as the plateau voltage, V
SGP
. Therefore, rise and fall
times may be approximated by the following:
t
r
= Q
2
x R
G
/(V
GG
− V
GSP
)
t
f
= Q
2
x R
G
/V
GSP
where
V
GG
= the gate drive voltage, which varies from zero to V
GG
R
G
= the gate drive resistance
and Q
2
and V
GSP
are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
d(on)
= R
G
C
iss
In [V
GG
/(V
GG
− V
GSP
)]
t
d(off)
= R
G
C
iss
In (V
GG
/V
GSP
)
The capacitance (C
iss
) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating t
d(on)
and is read at a voltage corresponding to the
on−state when calculating t
d(off)
.
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse
recovery characteristics which play a major role in
determining switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier
device, therefore it has a finite reverse recovery time, t
rr
, due
to the storage of minority carrier charge, Q
RR
, as shown in
the typical reverse recovery wave form of Figure 11. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery
further increases switching losses. Therefore, one would
like a diode with short t
rr
and low Q
RR
specifications to
minimize these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current
ringing. The mechanisms at work are finite irremovable
circuit parasitic inductances and capacitances acted upon by
high di/dts. The diode’s negative di/dt during t
a
is directly
controlled by the device clearing the stored charge.
However, the positive di/dt during t
b
is an uncontrollable
diode characteristic and is usually the culprit that induces
current ringing. Therefore, when comparing diodes, the
ratio of t
b
/t
a
serves as a good indicator of recovery
abruptness and thus gives a comparative estimate of
probable noise generated. A ratio of 1 is considered ideal and
values less than 0.5 are considered snappy.
Compared to ON Semiconductor standard cell density
low voltage MOSFETs, high cell density MOSFET diodes
are faster (shorter t
rr
), have less stored charge and a softer
reverse recovery characteristic. The softness advantage of
the high cell density diode means they can be forced through
reverse recovery at a higher di/dt than a standard cell
MOSFET diode without increasing the current ringing or the
noise generated. In addition, power dissipation incurred
from switching the diode will be less due to the shorter
recovery time and lower switching losses.
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4
MMDF3N06HD
Standard Cell Density
t
rr
I S , SOURCE CURRENT
High Cell Density
t
rr
t
b
t
a
t, TIME
Figure 7. Reverse Recovery Time (t
rr
)
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (T
C
) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(I
DM
) nor rated voltage (V
DSS
) is exceeded, and that the
transition time (t
r
, t
f
) does not exceed 10
µs.
In addition the
total power averaged over a complete switching cycle must
not exceed (T
J(MAX)
− T
C
)/(R
θJC
).
A power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and must be adjusted for operating
conditions differing from those specified. Although industry
practice is to rate in terms of energy, avalanche energy
capability is not a constant. The energy rating decreases
non−linearly with an increase of peak current in avalanche
and peak junction temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (I
DM
), the energy rating is specified at rated
continuous current (I
D
), in accordance with industry
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 9). Maximum
energy at currents below rated continuous I
D
can safely be
assumed to equal the values indicated.
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