P-Channel Enhancement Mode Field Effect Transistor
FEATURES
-55V, -50A, R
DS(ON)
= 23mΩ @V
GS
= 10V.
R
DS(ON)
= 28mΩ @V
GS
= 4.5V.
Super high dense cell design for extremely low R
DS(ON)
.
High power and current handing capability.
Lead-free plating ; RoHS compliant.
TO-220 & TO-263 package.
D
CEP5175/CEB5175
PRELIMINARY
D
G
G
D
S
S
CEB SERIES
TO-263(DD-PAK)
G
CEP SERIES
TO-220
S
ABSOLUTE MAXIMUM RATINGS
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current-Continuous @ T
C
= 25 C
@ T
C
= 100 C
Drain Current-Pulsed
a
Maximum Power Dissipation @ T
C
= 25 C
- Derate above 25 C
Operating and Store Temperature Range
Tc = 25 C unless otherwise noted
Symbol
V
DS
V
GS
I
D
I
DM
P
D
T
J
,T
stg
Limit
-55
Units
V
V
A
A
A
W
W/ C
C
±
20
-50
-32
-200
96
0.77
-55 to 150
Thermal Characteristics
Parameter
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient
Symbol
R
θJC
R
θJA
Limit
1.3
62.5
Units
C/W
C/W
This is preliminary information on a new product in development now .
Details are subject to change without notice .
1
Rev 1. 2014.Apr
http://www.cetsemi.com
CEP5175/CEB5175
Electrical Characteristics
Parameter
Off Characteristics
Drain-Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate Body Leakage Current, Forward
Gate Body Leakage Current, Reverse
On Characteristics
Static Drain-Source
On-Resistance
Dynamic Characteristics
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Switching Characteristics
c
Turn-On Delay Time
Turn-On Rise Time
Turn-Off Delay Time
Turn-Off Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Drain-Source Diode Forward Current
Drain-Source Diode Forward Voltage
b
t
d(on)
t
r
t
d(off)
t
f
Q
g
Q
gs
Q
gd
I
S
V
SD
V
GS
= 0V, I
S
= -20A
V
DS
= -45V, I
D
= -20A,
V
GS
= -4.5V
V
DD
= -45V, I
D
= -20A,
V
GS
= -10V, R
GEN
= 6Ω
18
10
175
60
35
12
16
-50
-1.2
ns
ns
ns
ns
nC
nC
nC
A
V
c
b
Tc = 25 C unless otherwise noted
Symbol
BV
DSS
I
DSS
I
GSSF
I
GSSR
V
GS(th)
R
DS(on)
C
iss
C
oss
C
rss
Test Condition
V
GS
= 0V, I
D
= -250µA
V
DS
= -55V, V
GS
= 0V
V
GS
= 20V, V
DS
= 0V
V
GS
= -20V, V
DS
= 0V
V
GS
= V
DS
, I
D
= -250µA
V
GS
= -10V, I
D
= -20A
V
GS
= -4.5V, I
D
= -10A
-1
18
20
3435
315
155
Min
-55
-1
100
-100
-3
23
28
Typ
Max
Units
V
µA
nA
nA
V
mΩ
mΩ
pF
pF
pF
Gate Threshold Voltage
V
DS
= -25V, V
GS
= 0V,
f = 1.0 MHz
Drain-Source Diode Characteristics and Maximun Ratings
Notes :
a.Repetitive Rating : Pulse width limited by maximum junction temperature.
b.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2%.
c.Guaranteed by design, not subject to production testing.
2
CEP5175/CEB5175
50
75
-I
D
, Drain Current (A)
30
20
10
0
-I
D
, Drain Current (A)
40
-V
GS
=10,8,6,4V
60
45
30
25 C
15
0
T
J
=125 C
-55 C
2.4
3.2
4
4.8
-V
GS
=3V
0
1.5
3
4.5
6
7.5
9
0
0.8
1.6
-V
DS
, Drain-to-Source Voltage (V)
Figure 1. Output Characteristics
3600
3000
2400
1800
1200
600
0
Crss
0
5
10
15
20
25
Coss
Ciss
2.2
1.9
1.6
1.3
1.0
0.7
0.4
-100
-V
GS
, Gate-to-Source Voltage (V)
Figure 2. Transfer Characteristics
I
D
=-20A
V
GS
=-10V
R
DS(ON),
Normalized
R
DS(ON)
, On-Resistance(Ohms)
C, Capacitance (pF)
-50
0
50
100
150
200
-V
DS
, Drain-to-Source Voltage (V)
Figure 3. Capacitance
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
-50
V
DS
=V
GS
10
3
T
J
, Junction Temperature( C)
Figure 4. On-Resistance Variation
with Temperature
-I
S
, Source-drain current (A)
V
GS
=0V
V
TH
, Normalized
Gate-Source Threshold Voltage
I
D
=-250µA
10
2
10
1
-25
0
25
50
75
100
125
150
10
0
0.3
0.6
0.9
1.2
1.5
1.8
T
J
, Junction Temperature( C)
Figure 5. Gate Threshold Variation
with Temperature
-V
SD
, Body Diode Forward Voltage (V)
Figure 6. Body Diode Forward Voltage
Variation with Source Current
3
CEP5175/CEB5175
V
GS
, Gate to Source Voltage (V)
10 V =-45V
DS
I
D
=-20A
10
3
I
D
, Drain Current (A)
8
6
4
2
0
10
2
100µs
1ms
10ms
DC
10
1
10
0
0
20
40
60
80
10
-1
10
-1
10
0
10
1
10
2
Qg, Total Gate Charge (nC)
Figure 7. Gate Charge
V
DD
t
on
V
IN
V
GS
R
GEN
G
R
L
D
V
OUT
t
d(on)
V
OUT
10%
V
DS
, Drain-Source Voltage (V)
Figure 8. Maximum Safe
Operating Area
t
off
t
r
90%
t
d(off)
90%
10%
t
f
INVERTED
90%
S
V
IN
50%
10%
50%
PULSE WIDTH
Figure 9. Switching Test Circuit
Figure 10. Switching Waveforms
r(t),Normalized Effective
Transient Thermal Impedance
10
0
D=0.5
0.2
10
-1
0.1
0.05
0.02
0.01
Single Pulse
P
DM
t
1
t
2
10
-2
1. R
θJC
(t)=r (t) * R
θJC
2. R
θJC
=See Datasheet
3. T
JM-
T
C
= P* R
θJC
(t)
4. Duty Cycle, D=t1/t2
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
Square Wave Pulse Duration (sec)
Figure 11. Normalized Thermal Transient Impedance Curve
4
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