Bt819A/817A/815A
VideoStream™ Decoders
Bt819A – Video Capture Processor for
TV/VCR Analog Input
Bt817A – Composite Video and S-Video Decoder
Bt815A – Composite Video Decoder
The Bt819A, Bt817A and Bt815A VideoStream Decoders are a family of single-
chip, pin and register compatible, composite NTSC/PAL video and S-video
decoders. Low operating power consumption and power down capability make
them ideal low-cost solutions for PC video capture applications on both desktop
and portable system platforms. They support square pixel and CCIR601 resolu-
tions for both NTSC and PAL. They have a flexible pixel port which supports a
variety of system interface configurations, and they are offered in both a 100-pin
PQFP and 100-pin TQFP.
Distinguishing Features
• Single-Chip Composite/S-Video
NTSC/PAL to YCrCb Digitizer
TM
• On-Chip Ultralock
• Square Pixel and CCIR601 Resolu-
tion for NTSC and PAL
• Chroma Comb Filtering
• Arbitrary Horizontal Scaling and
Vertical Scaling (using line store)
• Arbitrary Temporal Decimation
for a Reduced Frame-Rate Video
Sequence
• Programmable Hue, Brightness,
Saturation, and Contrast
• User-Programmable Cropping of
the Video Window
• 2x Oversampling to Simplify
External Analog Filtering
• Two-Wire I
2
C Bus Interface
• On-Chip 40-Pixel-Deep
Asynchronous Output FIFO
• 8- or 16-Bit Pixel Interface
• YCrCb (4:2:2) Output Format
• Software Selectable Three-Input
Analog Mux
• Auto NTSC/PAL Format Detect
• Automatic Gain Control
• IEEE 1149.1 (JTAG) Interface
• 100-Pin PQFP and TQFP Packages
Functional Block Diagram
XT0
MUX0
MUX1
MUX2
MUXOUT
SYNCDET
REFOUT
YREF+
YIN
YREF–
CREF+
CIN
CREF–
XT1
A
NALOG
M
UX
U
LTRALOCK
TM
AND
I
2
C
JTAG
FIFO
AND
O
UTPUT
F
ORMATTING
V
IDEO
T
IMING
AGC
D
ECIMATION
LPF
C
LOCK
G
ENERATION
V
IDEO
T
IMING
U
NIT
40 MH
Z
ADC
L
UMA
-C
HROMA
S
EPARATION
AND
O
UTPUT
C
ONTROL
40 MH
Z
ADC
C
HROMA
D
EMODULATION
S
PATIAL AND
T
EMPORAL
S
CALING
Related Products
16
O
UTPUT
D
ATA
• Bt812, Bt858, Bt855,
Bt856, Bt857
• Bt851
Applications
•
•
•
•
•
•
Multimedia
Image Processing
Desktop Video
Video Phone
Teleconferencing
Interactive Video
Ordering Information
Model Number
Bt819AKPF
Bt819AKTF
Bt817AKPF
Bt817AKTF
Bt815AKPF
Package
100-pin PQFP
100-pin TQFP
100-pin PQFP
100-pin TQFP
100-pin PQFP
Ambient Temperature Range
0˚C to +70˚C
0˚C to +70˚C
0˚C to +70˚C
0˚C to +70˚C
0˚C to +70˚C
Copyright © 1996 Rockwell Semiconductor Systems. All rights reserved.
Print date: September, 1996
Rockwell reserves the right to make changes to its products or specifications to improve performance, reliability, or
manufacturability. Information furnished by Rockwell Semiconductor Systems is believed to be accurate and reliable. However, no
responsibility is assumed by Rockwell Semiconductor Systems for its use; nor for any infringement of patents or other rights of
third parties which may result from its use. No license is granted by its implication or otherwise under any patent or patent rights of
Rockwell Semiconductor Systems.
Rockwell products are not designed or intended for use in life support appliances, devices, or systems where malfunction of a
Rockwell product can reasonably be expected to result in personal injury or death. Rockwell customers using or selling Rockwell
products for use in such applications do so at their own risk and agree to fully indemnify Rockwell for any damages resulting from
such improper use or sale.
Bt is a registered trademark of Rockwell Semiconductor Systems. Product names or services listed in this publication are for
identification purposes only, and may be trademarks or registered trademarks of their respective companies. All other marks
mentioned herein are the property of their respective holders.
Specifications are subject to change without notice.
PRINTED IN THE UNITED STATES OF AMERICA
T
ABLE OF
C
ONTENTS
List of Figures
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii
List of Tables
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
Functional Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Functional Overview
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Bt819A Video Capture Processor for TV/VCR Analog Input. . . . . . . . . . . . . . . . . . . .
Bt817A Composite/S-Video Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bt815A Composite Video Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bt819A Architecture and Partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UltraLock
™
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Scaling and Cropping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
2
C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
1
1
2
2
3
3
3
4
Pin Descriptions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Assignments
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
UltraLock
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
The Challenge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Operation Principles of UltraLock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Y/C Separation and Chroma Demodulation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Video Scaling, Cropping, and Temporal Decimation
. . . . . . . . . . . . . . . . . . . . . . . . . . 19
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Horizontal and Vertical Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Luminance Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chrominance Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Scaling Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Image Cropping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cropping Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temporal Decimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The Hue Adjust Register (HUE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The Contrast Adjust Register (CONTRAST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The Saturation Adjust Registers (SAT_U, SAT_V) . . . . . . . . . . . . . . . . . . . . . . . . . .
The Brightness Register (BRIGHT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
21
21
22
22
24
26
27
29
29
29
29
iii
Video Adjustments
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Bt819A/7A/5A
Electrical Interfaces
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Input Interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Analog Signal Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiplexer Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Autodetection of NTSC or PAL Video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash A/D Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A/D Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Automatic Gain Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Crystal Inputs and Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2X Oversampling and Input Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
YCrCb Pixel Stream Format, SPI Mode 8- and 16-bit Formats. . . . . . . . . . . . . . . . .
Synchronous Pixel Interface (SPI, Mode 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronous Pixel Interface (SPI, Mode 2, ByteStream) . . . . . . . . . . . . . . . . . . . . .
CCIR 601 Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Asynchronous Pixel Interface (API) (Bt819A Only) . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode A: FIFO Controlled by Bt819A (Bt819A Only) . . . . . . . . . . . . . . . . . . . . . . . . .
Mode B: FIFO Controlled by System (Bt819A Only) . . . . . . . . . . . . . . . . . . . . . . . . .
Asynchronous Pixel Interface Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Starting and Stopping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Addressing the Bt819A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reading and Writing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Need for Functional Verification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JTAG Approach to Testability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Optional Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Verification with the Tap Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
31
31
32
32
32
32
36
37
37
38
40
41
45
45
46
48
52
52
53
55
56
56
56
57
Output Interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
I
2
C Interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
JTAG Interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
PC Board Layout Considerations
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Ground Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Latch-up Avoidance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
61
62
62
62
62
62
Schematics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
iv
Bt819A/7A/5A
Control Register Definitions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
0x00 — Device Status Register (STATUS)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
0x01 — Input Format Register (IFORM)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
0x02 — Temporal Decimation Register (TDEC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
0x03 — MSB Cropping Register (CROP)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
0x04 — Vertical Delay Register, Lower Byte (VDELAY_LO)
. . . . . . . . . . . . . . . . . . . . 72
0x05 — Vertical Active Register, Lower Byte (VACTIVE_LO)
. . . . . . . . . . . . . . . . . . 73
0x06 — Horizontal Delay Register, Lower Byte (HDELAY_LO)
. . . . . . . . . . . . . . . . . 73
0x07 — Horizontal Active Register, Lower Byte (HACTIVE_LO)
. . . . . . . . . . . . . . . . 73
0x08 — Horizontal Scaling Register, Upper Byte (HSCALE_HI)
. . . . . . . . . . . . . . . . 74
0x09 — Horizontal Scaling Register, Lower Byte (HSCALE_LO)
. . . . . . . . . . . . . . . 74
0x0A — Brightness Control Register (BRIGHT)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
0x0B — Miscellaneous Control Register (CONTROL)
. . . . . . . . . . . . . . . . . . . . . . . . . 76
0x0C — Luma Gain Register, Lower Byte (CONTRAST_LO)
. . . . . . . . . . . . . . . . . . . 77
0x0D — Chroma (U) Gain Register, Lower Byte (SAT_U_LO)
. . . . . . . . . . . . . . . . . . 78
0x0E — Chroma (V) Gain Register, Lower Byte (SAT_V_LO)
. . . . . . . . . . . . . . . . . . 79
0x0F — Hue Control Register (HUE)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
0x10 — Reserved
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
0x11 — Reserved
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
0x12 — Output Format Register (OFORM)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
0x13 — Vertical Scaling Register, Upper Byte (VSCALE_HI)
. . . . . . . . . . . . . . . . . . . 84
0x14 — Vertical Scaling Register, Lower Byte (VSCALE_LO)
. . . . . . . . . . . . . . . . . . 85
0x15 — Test Control Register (TEST)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
0x16 — Video Timing Polarity Register (VPOLE)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
0x17 — ID Code Register (IDCODE)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
0x18 — AGC Delay Register (ADELAY)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
0x19 — Burst Delay Register (BDELAY)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
0x1A — ADC Interface Register (ADC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
0x1B to 0x1E — Reserved Registers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
0x1F — Software Reset Register (SRESET)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
v
stm32/stm8
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