74LVT125; 74LVTH125
3.3 V quad buffer; 3-state
Rev. 06 — 6 March 2006
Product data sheet
1. General description
The 74LVT125; 74LVTH125 is a high-performance BiCMOS product designed for V
CC
operation at 3.3 V.
This device combines low static and dynamic power dissipation with high speed and high
output drive. The 74LVT125; 74LVTH125 device is a quad buffer that is ideal for driving
bus lines. The device features four output enable inputs (1OE, 2OE, 3OE and 4OE), each
controlling one of the 3-state outputs.
2. Features
I
I
I
I
I
I
I
I
I
I
Quad bus interface
3-state buffers
Output capability: +64 mA and
−32
mA
TTL input and output switching levels
Input and output interface capability to systems at 5 V supply
Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs
Live insertion and extraction permitted
No bus current loading when output is tied to 5 V bus
Power-up 3-state
Latch-up protection:
N
JESD78: exceeds 500 mA
I
ESD protection:
N
MIL STD 883 method 3015: exceeds 2000 V
N
Machine model: exceeds 200 V
3. Quick reference data
Table 1.
Quick reference data
GND = 0 V; T
amb
= 25
°
C.
Symbol Parameter
t
PLH
t
PHL
LOW-to-HIGH propagation
delay nA to nY
Conditions
C
L
= 50 pF; V
CC
= 3.3 V
Min
-
-
Typ
2.7
2.9
Max
-
-
Unit
ns
ns
HIGH-to-LOW propagation C
L
= 50 pF; V
CC
= 3.3 V
delay nA to nY
Philips Semiconductors
74LVT125; 74LVTH125
3.3 V quad buffer; 3-state
Table 1.
Quick reference data
…continued
GND = 0 V; T
amb
= 25
°
C.
Symbol Parameter
C
i
C
o
I
CC
input capacitance
output capacitance
quiescent supply current
Conditions
V
I
= 0 V or 3.0 V
outputs disabled;
V
O
= 0 V or 3.0 V
outputs disabled;
V
CC
= 3.6 V
Min
-
-
-
Typ
4
8
0.13
Max
-
-
-
Unit
pF
pF
mA
4. Ordering information
Table 2.
Ordering information
Package
Temperature range Name
74LVT125D
74LVT125DB
74LVT125PW
74LVT125BQ
−40 °C
to +85
°C
−40 °C
to +85
°C
−40 °C
to +85
°C
−40 °C
to +85
°C
SO14
SSOP14
TSSOP14
DHVQFN14
Description
plastic small outline package; 14 leads;
body width 3.9 mm
plastic shrink small outline package; 14 leads;
body width 5.3 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
Version
SOT108-1
SOT337-1
SOT402-1
Type number
plastic dual in-line compatible thermal enhanced very SOT762-1
thin quad flat package; no leads; 14 terminals;
body 2.5
×
3
×
0.85 mm
plastic small outline package; 14 leads;
body width 3.9 mm
plastic shrink small outline package; 14 leads;
body width 5.3 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT108-1
SOT337-1
SOT402-1
74LVTH125D
74LVTH125DB
74LVTH125PW
74LVTH125BQ
−40 °C
to +85
°C
−40 °C
to +85
°C
−40 °C
to +85
°C
−40 °C
to +85
°C
SO14
SSOP14
TSSOP14
DHVQFN14
plastic dual in-line compatible thermal enhanced very SOT762-1
thin quad flat package; no leads; 14 terminals;
body 2.5
×
3
×
0.85 mm
74LVT_LVTH125_6
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 06 — 6 March 2006
2 of 16
Philips Semiconductors
74LVT125; 74LVTH125
3.3 V quad buffer; 3-state
5. Functional diagram
2
1
5
4
9
10
12
13
1A
1OE
2A
2OE
3A
3OE
1Y
3
2
1
1
3
EN1
6
2Y
6
5
4
3Y
8
9
8
10
12
4A
4OE
4Y
11
13
mna229
11
mna228
Fig 1. Logic symbol
Fig 2. IEC logic symbol
nA
nY
nOE
mna227
Fig 3. Logic diagram
6. Pinning information
6.1 Pinning
1OE
2
3
4
5
6
7
GND
3Y
8
1
1A
1Y
2OE
2A
2Y
GND
2
3
4
5
6
7
001aac476
1OE
1
14 V
CC
13 4OE
12 4A
terminal 1
index area
1A
1Y
2OE
2A
2Y
14 V
CC
13 4OE
12 4A
11 4Y
10 3OE
9
3A
125
11 4Y
10 3OE
9
8
3A
3Y
125
GND
(1)
001aac477
Transparent top view
(1) The die substrate is attached to the
exposed die pad using conductive die
attach material. It can not be used as
a supply pin or input.
Fig 4. Pin configuration SO14, SSOP14
and TSSOP14
74LVT_LVTH125_6
Fig 5. Pin configuration DHVQFN14
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 06 — 6 March 2006
3 of 16
Philips Semiconductors
74LVT125; 74LVTH125
3.3 V quad buffer; 3-state
6.2 Pin description
Table 3.
Symbol
1OE
1A
1Y
2OE
2A
2Y
GND
3Y
3A
3OE
4Y
4A
4OE
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Description
1 output enable input (active LOW)
1 data input
1 data output
2 output enable input (active LOW)
2 data input
2 data output
ground (0 V)
3 data output
3 data input
3 output enable input (active LOW)
4 data output
4 data input
4 output enable input (active LOW)
supply voltage
7. Functional description
7.1 Function table
Table 4.
Control
nOE
L
H
[1]
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high-impedance OFF-state.
Function table
[1]
Input
nA
L
H
X
Output
nY
L
H
Z
74LVT_LVTH125_6
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 06 — 6 March 2006
4 of 16
Philips Semiconductors
74LVT125; 74LVTH125
3.3 V quad buffer; 3-state
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
Symbol Parameter
V
CC
V
I
V
O
I
IK
I
OK
I
O
T
stg
T
j
[1]
[2]
Conditions
[1]
Min
−0.5
−0.5
−0.5
-
-
-
-
−65
[2]
Max
+4.6
+7.0
+7.0
−50
−50
128
−64
+150
150
Unit
V
V
V
mA
mA
mA
mA
°C
°C
supply voltage
input voltage
output voltage
input clamping current
output clamping current
output current
storage temperature
junction temperature
output in OFF-state or
HIGH-state
V
I
< 0 V
V
O
< 0 V
output in LOW-state
output in HIGH-state
[1]
-
The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings
are observed.
The performance capability of a high-performance integrated circuit in conjunction with its thermal
environment can create junction temperatures which are detrimental to reliability.
9. Recommended operating conditions
Table 6.
V
CC
V
I
V
IH
V
IL
I
OH
I
OL
Recommended operating conditions
Conditions
Min
2.7
0
2.0
-
-
none
current duty cycle
≤
50 %;
f
≥
1 kHz
∆t/∆V
T
amb
input transition rise and
fall rate
ambient temperature
in free air
-
-
0
−40
Typ
-
-
-
-
-
-
-
-
-
Max
3.6
5.5
-
0.8
−32
32
64
10
+85
Unit
V
V
V
V
mA
mA
mA
ns/V
°C
supply voltage
input voltage
HIGH-state input voltage
LOW-state input voltage
HIGH-state output current
LOW-state output current
Symbol Parameter
74LVT_LVTH125_6
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 06 — 6 March 2006
5 of 16
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